1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2018 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan #ifndef _SMU_HELPER_H_
24e098bc96SEvan Quan #define _SMU_HELPER_H_
25e098bc96SEvan Quan
26e098bc96SEvan Quan struct pp_atomctrl_voltage_table;
27e098bc96SEvan Quan struct pp_hwmgr;
28e098bc96SEvan Quan struct phm_ppt_v1_voltage_lookup_table;
29e098bc96SEvan Quan struct Watermarks_t;
30e098bc96SEvan Quan struct pp_wm_sets_with_clock_ranges_soc15;
31e098bc96SEvan Quan
32e098bc96SEvan Quan uint8_t convert_to_vid(uint16_t vddc);
33e098bc96SEvan Quan uint16_t convert_to_vddc(uint8_t vid);
34e098bc96SEvan Quan
35e098bc96SEvan Quan struct watermark_row_generic_t {
36e098bc96SEvan Quan uint16_t MinClock;
37e098bc96SEvan Quan uint16_t MaxClock;
38e098bc96SEvan Quan uint16_t MinUclk;
39e098bc96SEvan Quan uint16_t MaxUclk;
40e098bc96SEvan Quan
41e098bc96SEvan Quan uint8_t WmSetting;
42e098bc96SEvan Quan uint8_t Padding[3];
43e098bc96SEvan Quan };
44e098bc96SEvan Quan
45e098bc96SEvan Quan struct watermarks {
46e098bc96SEvan Quan struct watermark_row_generic_t WatermarkRow[2][4];
47e098bc96SEvan Quan uint32_t padding[7];
48e098bc96SEvan Quan };
49e098bc96SEvan Quan
50e098bc96SEvan Quan int phm_copy_clock_limits_array(
51e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
52e098bc96SEvan Quan uint32_t **pptable_info_array,
53e098bc96SEvan Quan const uint32_t *pptable_array,
54e098bc96SEvan Quan uint32_t power_saving_clock_count);
55e098bc96SEvan Quan
56e098bc96SEvan Quan int phm_copy_overdrive_settings_limits_array(
57e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
58e098bc96SEvan Quan uint32_t **pptable_info_array,
59e098bc96SEvan Quan const uint32_t *pptable_array,
60e098bc96SEvan Quan uint32_t od_setting_count);
61e098bc96SEvan Quan
62e098bc96SEvan Quan extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
63e098bc96SEvan Quan uint32_t index,
64e098bc96SEvan Quan uint32_t value, uint32_t mask);
65e098bc96SEvan Quan extern int phm_wait_for_indirect_register_unequal(
66e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
67e098bc96SEvan Quan uint32_t indirect_port, uint32_t index,
68e098bc96SEvan Quan uint32_t value, uint32_t mask);
69e098bc96SEvan Quan
70e098bc96SEvan Quan
71e098bc96SEvan Quan extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
72e098bc96SEvan Quan extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
73e098bc96SEvan Quan extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
74e098bc96SEvan Quan
75e098bc96SEvan Quan extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
76e098bc96SEvan Quan extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
77e098bc96SEvan Quan extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
78e098bc96SEvan Quan extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
79e098bc96SEvan Quan extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
80e098bc96SEvan Quan extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
81e098bc96SEvan Quan extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
82e098bc96SEvan Quan extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
83e098bc96SEvan Quan extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
84e098bc96SEvan Quan uint32_t voltage);
85e098bc96SEvan Quan extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
86e098bc96SEvan Quan extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
87e098bc96SEvan Quan extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
88e098bc96SEvan Quan extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
89e098bc96SEvan Quan uint16_t virtual_voltage_id, int32_t *sclk);
90e098bc96SEvan Quan extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
91e098bc96SEvan Quan extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
92e098bc96SEvan Quan extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
93e098bc96SEvan Quan
94e098bc96SEvan Quan extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
95e098bc96SEvan Quan uint32_t sclk, uint16_t id, uint16_t *voltage);
96e098bc96SEvan Quan
97e098bc96SEvan Quan extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
98e098bc96SEvan Quan
99e098bc96SEvan Quan extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
100e098bc96SEvan Quan uint32_t value, uint32_t mask);
101e098bc96SEvan Quan
102e098bc96SEvan Quan extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
103e098bc96SEvan Quan uint32_t indirect_port,
104e098bc96SEvan Quan uint32_t index,
105e098bc96SEvan Quan uint32_t value,
106e098bc96SEvan Quan uint32_t mask);
107e098bc96SEvan Quan
108e098bc96SEvan Quan int phm_irq_process(struct amdgpu_device *adev,
109e098bc96SEvan Quan struct amdgpu_irq_src *source,
110e098bc96SEvan Quan struct amdgpu_iv_entry *entry);
111e098bc96SEvan Quan
112*e9c76719SAlex Deucher /*
113*e9c76719SAlex Deucher * Helper function to make sysfs_emit_at() happy. Align buf to
114*e9c76719SAlex Deucher * the current page boundary and record the offset.
115*e9c76719SAlex Deucher */
phm_get_sysfs_buf(char ** buf,int * offset)116*e9c76719SAlex Deucher static inline void phm_get_sysfs_buf(char **buf, int *offset)
117*e9c76719SAlex Deucher {
118*e9c76719SAlex Deucher if (!*buf || !offset)
119*e9c76719SAlex Deucher return;
120*e9c76719SAlex Deucher
121*e9c76719SAlex Deucher *offset = offset_in_page(*buf);
122*e9c76719SAlex Deucher *buf -= *offset;
123*e9c76719SAlex Deucher }
124*e9c76719SAlex Deucher
125e098bc96SEvan Quan int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
126e098bc96SEvan Quan
127e098bc96SEvan Quan void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
128e098bc96SEvan Quan uint8_t *frev, uint8_t *crev);
129e098bc96SEvan Quan
130e098bc96SEvan Quan int smu_get_voltage_dependency_table_ppt_v1(
131e098bc96SEvan Quan const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
132e098bc96SEvan Quan struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
133e098bc96SEvan Quan
134e098bc96SEvan Quan int smu_set_watermarks_for_clocks_ranges(void *wt_table,
135e098bc96SEvan Quan struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
136e098bc96SEvan Quan
137e098bc96SEvan Quan #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
138e098bc96SEvan Quan #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
139e098bc96SEvan Quan
140e098bc96SEvan Quan #define PHM_SET_FIELD(origval, reg, field, fieldval) \
141e098bc96SEvan Quan (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
142e098bc96SEvan Quan (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
143e098bc96SEvan Quan
144e098bc96SEvan Quan #define PHM_GET_FIELD(value, reg, field) \
145e098bc96SEvan Quan (((value) & PHM_FIELD_MASK(reg, field)) >> \
146e098bc96SEvan Quan PHM_FIELD_SHIFT(reg, field))
147e098bc96SEvan Quan
148e098bc96SEvan Quan
149e098bc96SEvan Quan /* Operations on named fields. */
150e098bc96SEvan Quan
151e098bc96SEvan Quan #define PHM_READ_FIELD(device, reg, field) \
152e098bc96SEvan Quan PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
153e098bc96SEvan Quan
154e098bc96SEvan Quan #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
155e098bc96SEvan Quan PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
156e098bc96SEvan Quan reg, field)
157e098bc96SEvan Quan
158e098bc96SEvan Quan #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
159e098bc96SEvan Quan PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
160e098bc96SEvan Quan reg, field)
161e098bc96SEvan Quan
162e098bc96SEvan Quan #define PHM_WRITE_FIELD(device, reg, field, fieldval) \
163e098bc96SEvan Quan cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
164e098bc96SEvan Quan cgs_read_register(device, mm##reg), reg, field, fieldval))
165e098bc96SEvan Quan
166e098bc96SEvan Quan #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
167e098bc96SEvan Quan cgs_write_ind_register(device, port, ix##reg, \
168e098bc96SEvan Quan PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
169e098bc96SEvan Quan reg, field, fieldval))
170e098bc96SEvan Quan
171e098bc96SEvan Quan #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
172e098bc96SEvan Quan cgs_write_ind_register(device, port, ix##reg, \
173e098bc96SEvan Quan PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
174e098bc96SEvan Quan reg, field, fieldval))
175e098bc96SEvan Quan
176e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
177e098bc96SEvan Quan phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
178e098bc96SEvan Quan
179e098bc96SEvan Quan
180e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
181e098bc96SEvan Quan PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
182e098bc96SEvan Quan
183e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
184e098bc96SEvan Quan PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
185e098bc96SEvan Quan << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
186e098bc96SEvan Quan
187e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
188e098bc96SEvan Quan phm_wait_for_indirect_register_unequal(hwmgr, \
189e098bc96SEvan Quan mm##port##_INDEX, index, value, mask)
190e098bc96SEvan Quan
191e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
192e098bc96SEvan Quan PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
193e098bc96SEvan Quan
194e098bc96SEvan Quan #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
195e098bc96SEvan Quan PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
196e098bc96SEvan Quan (fieldval) << PHM_FIELD_SHIFT(reg, field), \
197e098bc96SEvan Quan PHM_FIELD_MASK(reg, field))
198e098bc96SEvan Quan
199e098bc96SEvan Quan
200e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
201e098bc96SEvan Quan port, index, value, mask) \
202e098bc96SEvan Quan phm_wait_for_indirect_register_unequal(hwmgr, \
203e098bc96SEvan Quan mm##port##_INDEX_11, index, value, mask)
204e098bc96SEvan Quan
205e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
206e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
207e098bc96SEvan Quan
208e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
209e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
210e098bc96SEvan Quan (fieldval) << PHM_FIELD_SHIFT(reg, field), \
211e098bc96SEvan Quan PHM_FIELD_MASK(reg, field))
212e098bc96SEvan Quan
213e098bc96SEvan Quan
214e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
215e098bc96SEvan Quan port, index, value, mask) \
216e098bc96SEvan Quan phm_wait_on_indirect_register(hwmgr, \
217e098bc96SEvan Quan mm##port##_INDEX_11, index, value, mask)
218e098bc96SEvan Quan
219e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
220e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
221e098bc96SEvan Quan
222e098bc96SEvan Quan #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
223e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
224e098bc96SEvan Quan (fieldval) << PHM_FIELD_SHIFT(reg, field), \
225e098bc96SEvan Quan PHM_FIELD_MASK(reg, field))
226e098bc96SEvan Quan
227e098bc96SEvan Quan #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
228e098bc96SEvan Quan index, value, mask) \
229e098bc96SEvan Quan phm_wait_for_register_unequal(hwmgr, \
230e098bc96SEvan Quan index, value, mask)
231e098bc96SEvan Quan
232e098bc96SEvan Quan #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
233e098bc96SEvan Quan PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
234e098bc96SEvan Quan mm##reg, value, mask)
235e098bc96SEvan Quan
236e098bc96SEvan Quan #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
237e098bc96SEvan Quan PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
238e098bc96SEvan Quan (fieldval) << PHM_FIELD_SHIFT(reg, field), \
239e098bc96SEvan Quan PHM_FIELD_MASK(reg, field))
240e098bc96SEvan Quan
241e098bc96SEvan Quan #endif /* _SMU_HELPER_H_ */
242