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Searched refs:cci (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/hw/cxl/
H A Dcxl-mailbox-utils.c151 CXLCCI *cci) in cmd_tunnel_management_cmd() argument
204 if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_TYPE3)) { in cmd_tunnel_management_cmd()
205 CXLType3Dev *ct3d = CXL_TYPE3(cci->d); in cmd_tunnel_management_cmd()
211 } else if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_USP)) { in cmd_tunnel_management_cmd()
212 CXLUpstreamPort *usp = CXL_USP(cci->d); in cmd_tunnel_management_cmd()
259 CXLCCI *cci) in cmd_events_get_records() argument
261 CXLDeviceState *cxlds = &CXL_TYPE3(cci->d)->cxl_dstate; in cmd_events_get_records()
288 CXLCCI *cci) in cmd_events_clear_records() argument
290 CXLDeviceState *cxlds = &CXL_TYPE3(cci->d)->cxl_dstate; in cmd_events_clear_records()
309 CXLCCI *cci) in cmd_events_get_interrupt_policy() argument
[all …]
H A Dcxl-device-utils.c66 CXLCCI *cci = opaque; in mailbox_reg_read() local
68 if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) { in mailbox_reg_read()
69 cxl_dstate = &CXL_TYPE3(cci->intf)->cxl_dstate; in mailbox_reg_read()
70 } else if (object_dynamic_cast(OBJECT(cci->intf), in mailbox_reg_read()
72 cxl_dstate = &CXL_SWITCH_MAILBOX_CCI(cci->intf)->cxl_dstate; in mailbox_reg_read()
88 cci->bg.opcode); in mailbox_reg_read()
90 PERCENTAGE_COMP, cci->bg.complete_pct); in mailbox_reg_read()
92 RET_CODE, cci->bg.ret_code); in mailbox_reg_read()
100 qemu_mutex_lock(&cci->bg.lock); in mailbox_reg_read()
101 bgop = !(cci->bg.complete_pct == 100 || cci->bg.aborted); in mailbox_reg_read()
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H A Dswitch-mailbox-cci.c45 cswmb->cci = &usp->swcci; in cswbcci_realize()
46 cxl_device_register_block_init(OBJECT(pci_dev), cxl_dstate, cswmb->cci); in cswbcci_realize()
60 cxl_initialize_mailbox_swcci(cswmb->cci, DEVICE(pci_dev), in cswbcci_realize()
H A Dmeson.build9 'switch-mailbox-cci.c',
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dsoc.c111 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_early() local
116 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); in erratum_a008850_early()
127 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_post() local
133 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in erratum_a008850_post()
162 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in arch_soc_init() local
185 out_le32(&cci->slave[0].snoop_ctrl, in arch_soc_init()
187 out_le32(&cci->slave[1].snoop_ctrl, in arch_soc_init()
189 out_le32(&cci->slave[2].snoop_ctrl, in arch_soc_init()
191 out_le32(&cci->slave[4].snoop_ctrl, in arch_soc_init()
200 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); in arch_soc_init()
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/openbmc/qemu/include/hw/cxl/
H A Dcxl_device.h151 CXLCCI *cci);
274 CXLCCI *cci);
327 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
328 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
330 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
331 void cxl_destroy_cci(CXLCCI *cci);
332 void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256],
334 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
338 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
342 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
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/openbmc/u-boot/board/freescale/ls1012afrdm/
H A Dls1012afrdm.c160 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in board_init() local
168 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in board_init()
/openbmc/u-boot/board/freescale/ls1012ardb/
H A Dls1012ardb.c142 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in board_init() local
149 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in board_init()
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dsoc.c413 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_early() local
422 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); in erratum_a008850_early()
433 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_post() local
443 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in erratum_a008850_post()
593 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in fsl_lsch2_early_init_f() local
619 out_le32(&cci->slave[4].snoop_ctrl, in fsl_lsch2_early_init_f()
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a83t.dtsi69 cci-control-port = <&cci_control0>;
78 cci-control-port = <&cci_control0>;
87 cci-control-port = <&cci_control0>;
96 cci-control-port = <&cci_control0>;
107 cci-control-port = <&cci_control1>;
116 cci-control-port = <&cci_control1>;
125 cci-control-port = <&cci_control1>;
134 cci-control-port = <&cci_control1>;
373 cci@1790000 {
374 compatible = "arm,cci-400";
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H A Dsun9i-a80.dtsi66 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
84 cci-control-port = <&cci_control0>;
93 cci-control-port = <&cci_control0>;
102 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control1>;
120 cci-control-port = <&cci_control1>;
129 cci-control-port = <&cci_control1>;
488 cci: cci@1c90000 { label
489 compatible = "arm,cci-400";
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H A Dzynqmp.dtsi261 cci: cci@fd6e0000 { label
262 compatible = "arm,cci-400";
269 compatible = "arm,cci-400-pmu,r1";
/openbmc/u-boot/board/freescale/ls1012aqds/
H A Dls1012aqds.c120 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in board_init() local
126 out_le32(&cci->ctrl_ord, in board_init()
/openbmc/qemu/hw/mem/
H A Dcxl_type3.c911 &ct3d->cci); in ct3_realize()
997 cxl_destroy_cci(&ct3d->cci); in ct3_exit()