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Searched refs:cache_mem_registers (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c75 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); in cxl_cache_mem_read_reg()
76 return cregs->cache_mem_registers[offset / 4]; in cxl_cache_mem_read_reg()
95 uint32_t *cache_mem = cregs->cache_mem_registers; in dumb_hdm_handler()
131 QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); in cxl_cache_mem_write_reg()
135 value |= ~mask & cregs->cache_mem_registers[offset / 4]; in cxl_cache_mem_write_reg()
145 cregs->cache_mem_registers[offset / 4] = value; in cxl_cache_mem_write_reg()
/openbmc/qemu/hw/pci-bridge/
H A Dcxl_downstream.c38 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
H A Dcxl_root_port.c101 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
H A Dcxl_upstream.c89 uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
/openbmc/qemu/include/hw/cxl/
H A Dcxl_component.h224 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; member