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Searched refs:bypass (Results 1 – 25 of 317) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk… in rv1_dump_clk_registers() argument
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) in rv1_dump_clk_registers()
60 bypass->dcfclk_bypass = 0; in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) in rv1_dump_clk_registers()
71 bypass->dispclk_pypass = 0; in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) in rv1_dump_clk_registers()
77 bypass->dprefclk_bypass = 0; in rv1_dump_clk_registers()
/openbmc/qemu/docs/
H A Dbypass-iommu.txt8 is not flexible. We introduce this bypass iommu property to support
22 The bypass iommu feature support PXB host bridge and default main host
29 1. The following is the bypass iommu options:
34 (3) X86 default root bus bypass iommu:
46 - a default host bridge which bypass SMMUv3
48 - a pxb host bridge which bypass SMMUv3
60 - a default host bridge which bypass iommu
62 - a pxb host bridge which bypass iommu
73 The bypass iommu feature includes:
76 space for devices bypass iommu.
[all …]
/openbmc/linux/drivers/usb/misc/
H A Dusb3503.c49 struct gpio_desc *bypass; member
113 int rst, bypass, conn; in usb3503_switch_mode() local
119 bypass = 0; in usb3503_switch_mode()
124 bypass = 1; in usb3503_switch_mode()
130 bypass = 1; in usb3503_switch_mode()
143 if (hub->bypass) in usb3503_switch_mode()
144 gpiod_set_value_cansleep(hub->bypass, bypass); in usb3503_switch_mode()
262 if (IS_ERR(hub->bypass)) { in usb3503_probe()
263 err = PTR_ERR(hub->bypass); in usb3503_probe()
266 if (hub->bypass) in usb3503_probe()
[all …]
/openbmc/linux/drivers/regulator/
H A Danatop-regulator.c30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsmsc,usb3503.yaml37 bypass-gpios:
40 GPIO for bypass.
57 Specifies initial mode. 1 for Hub mode, 2 for standby mode and 3 for bypass mode.
58 In bypass mode the downstream port 3 is connected to the upstream port with low
91 bypass-gpios: false
95 - bypass-gpios
138 bypass-gpios = <&gpx3 6 1>;
/openbmc/qemu/hw/virtio/
H A Dvirtio-iommu.c49 bool bypass; member
88 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
94 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
354 if (domain->bypass != bypass) { in virtio_iommu_get_domain()
364 domain->bypass = bypass; in virtio_iommu_get_domain()
571 if (domain->bypass) { in virtio_iommu_map()
621 if (domain->bypass) { in virtio_iommu_unmap()
1009 out_config->bypass = dev_config->bypass; in virtio_iommu_get_config()
1027 if (in_config->bypass != dev_config->bypass) { in virtio_iommu_set_config()
1031 } else if (in_config->bypass != 0 && in_config->bypass != 1) { in virtio_iommu_set_config()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsram.h12 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
25 int bypass);
38 int bypass);
H A Dclkt2xxx_dpllcore.c114 u32 bypass = 0; in omap2_reprogram_dpllcore() local
162 bypass = 1; in omap2_reprogram_dpllcore()
169 bypass); in omap2_reprogram_dpllcore()
H A Dclkt2xxx_virt_prcm_set.c100 u32 cur_rate, done_rate, bypass = 0; in omap2_select_table_rate() local
135 bypass = 1; in omap2_select_table_rate()
153 bypass); in omap2_select_table_rate()
/openbmc/linux/include/trace/events/
H A Dbcache.h124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
179 __entry->nr_sector, __entry->writeback, __entry->bypass)
/openbmc/qemu/tests/qapi-schema/
H A Dtype-bypass-bad-gen.err1 type-bypass-bad-gen.json: In command 'foo':
2 type-bypass-bad-gen.json:2: flag 'gen' may only use false value
/openbmc/linux/drivers/md/bcache/
H A Dstats.c184 bool hit, bool bypass) in mark_cache_stats() argument
186 if (!bypass) in mark_cache_stats()
199 bool hit, bool bypass) in bch_mark_cache_accounting() argument
203 mark_cache_stats(&dc->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
204 mark_cache_stats(&c->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
/openbmc/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-i2c-devices-bq32k5 Description: Attribute for enable/disable the trickle charge bypass
7 enable/disable the Trickle charge FET bypass.
H A Dsysfs-bus-iio-filter-admv881810 - bypass -> bypass low pass filter, high pass filter and disable/unregister
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/
H A Dscp-firmware-juno.inc11 …install -D "${B}/${TYPE}/${FW_TARGETS}/bin/${SCP_PLATFORM}-bl1-bypass.bin" "${D}/firmware/${FW}_${…
12 …install -D "${B}/${TYPE}/${FW_TARGETS}/bin/${SCP_PLATFORM}-bl1-bypass.elf" "${D}/firmware/${FW}_${…
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-pll.c44 unsigned long bypass; in clk_pll_recalc_rate() local
47 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); in clk_pll_recalc_rate()
48 if (bypass & MAINPLL_BYPASS) in clk_pll_recalc_rate()
/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A Dbq25980.yaml54 ti,bypass-ovp-limit-microvolt:
61 ti,bypass-ocp-limit-microamp:
67 ti,bypass-enable:
69 description: Enables bypass mode at boot time
/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-hw.c122 bool *bypass) in mxc_isi_channel_set_scaling() argument
165 *bypass = in_size->height == out_size->height && in mxc_isi_channel_set_scaling()
211 bool *bypass) in mxc_isi_channel_set_csc() argument
256 *bypass = !cscen; in mxc_isi_channel_set_csc()
306 bool bypass) in mxc_isi_channel_set_control() argument
321 if (bypass) in mxc_isi_channel_set_control()
540 mxc_isi_pipe_irq_t irq_handler, bool bypass) in mxc_isi_channel_acquire() argument
558 | (!bypass ? MXC_ISI_CHANNEL_RES_LINE_BUF : 0); in mxc_isi_channel_acquire()
592 int mxc_isi_channel_chain(struct mxc_isi_pipe *pipe, bool bypass) in mxc_isi_channel_chain() argument
/openbmc/linux/drivers/clk/at91/
H A Dsckc.c122 bool bypass, in at91_clk_register_slow_osc() argument
148 if (bypass) in at91_clk_register_slow_osc()
378 bool bypass; in at91sam9x5_sckc_register() local
398 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
402 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
411 &parent_data, 1200000, bypass, bits); in at91sam9x5_sckc_register()
479 bool bypass; in of_sam9x60_sckc_setup() local
496 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
498 &parent_data, 5000000, bypass, in of_sam9x60_sckc_setup()
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rt4803.yaml15 supports boost and auto bypass mode that depends on the difference between the
17 transform to boost mode. Otherwise, turn on bypass switch to enter bypass mode.
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt7 (reference clock and bypass clock), with digital phase locked
38 and second entry bypass clock
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
81 ti,low-power-bypass;
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-asxx-defs.h200 uint64_t bypass:1; member
202 uint64_t bypass:1;
469 uint64_t bypass:1; member
475 uint64_t bypass:1;
493 uint64_t bypass:1; member
503 uint64_t bypass:1;
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dactions,atc260x.yaml68 regulator-allow-bypass: true
87 regulator-allow-bypass: true
103 regulator-allow-bypass: false
115 regulator-allow-bypass: false
/openbmc/linux/drivers/pwm/
H A Dpwm-sun4i.c173 bool *bypass) in sun4i_pwm_calculate() argument
180 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
187 if (*bypass) in sun4i_pwm_calculate()
241 bool bypass; in sun4i_pwm_apply() local
254 &bypass); in sun4i_pwm_apply()
266 if (bypass) { in sun4i_pwm_apply()

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