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Searched refs:bit_off (Results 1 – 25 of 36) sorted by relevance

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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
136 reg &= ~(3 << bit_off); in dc_set_mux()
137 reg |= (selector << bit_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
154 if ((reg & (3 << bit_off)) != 0) in dc_pmx_request_gpio()
178 drive &= ~BIT(bit_off); in dc_gpio_direction_input()
200 drive |= BIT(bit_off); in dc_gpio_direction_output()
216 return !!(input & BIT(bit_off)); in dc_gpio_get()
230 output |= BIT(bit_off); in dc_gpio_set()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c60 u32 bit_off; in dpu_hw_set_mem_type() local
78 bit_off = (xin_id & 0x7) * 4; in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
91 u32 bit_off; in dpu_hw_set_limit_conf() local
99 bit_off = (xin_id % 4) * 8; in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
112 u32 bit_off; in dpu_hw_get_limit_conf() local
121 bit_off = (xin_id % 4) * 8; in dpu_hw_get_limit_conf()
[all …]
H A Ddpu_hw_top.c70 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local
83 bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off; in dpu_hw_setup_clk_force_ctrl()
88 new_val = reg_val | BIT(bit_off); in dpu_hw_setup_clk_force_ctrl()
90 new_val = reg_val & ~BIT(bit_off); in dpu_hw_setup_clk_force_ctrl()
94 clk_forced_on = !(reg_val & BIT(bit_off)); in dpu_hw_setup_clk_force_ctrl()
/openbmc/linux/mm/
H A Dpercpu.c462 *bit_off = pcpu_block_off_to_off(i, *bit_off); in pcpu_next_fit_region()
748 int bit_off, bits; in pcpu_chunk_refresh_hint() local
763 pcpu_block_update(chunk_md, bit_off, bit_off + bits); in pcpu_chunk_refresh_hint()
928 bit_off, in pcpu_block_update_hint_alloc()
929 bit_off + bits)) in pcpu_block_update_hint_alloc()
940 bit_off, in pcpu_block_update_hint_alloc()
941 bit_off + bits)) in pcpu_block_update_hint_alloc()
1131 bit_off = next_off; in pcpu_find_block_fit()
1138 return bit_off; in pcpu_find_block_fit()
1235 if (bit_off >= end) in pcpu_alloc_area()
[all …]
/openbmc/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c113 u32 bit_off; in sppctl_get_reg_and_bit_offset() local
117 bit_off = offset % 32; in sppctl_get_reg_and_bit_offset()
119 return bit_off; in sppctl_get_reg_and_bit_offset()
124 u32 bit_off; in sppctl_get_moon_reg_and_bit_offset() local
133 bit_off = offset % 16; in sppctl_get_moon_reg_and_bit_offset()
135 return bit_off; in sppctl_get_moon_reg_and_bit_offset()
140 u32 bit_off; in sppctl_prep_moon_reg_and_offset() local
263 u32 reg_off, bit_off, reg; in sppctl_first_get() local
298 u32 reg_off, bit_off, reg; in sppctl_master_get() local
321 reg |= BIT(bit_off); in sppctl_first_master_set()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_3_0_msm8998.h29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
37 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
38 [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
H A Ddpu_9_0_sm8550.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
35 [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
36 [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
[all …]
H A Ddpu_7_0_sm8350.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_6_0_sm8250.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_4_0_sdm845.h29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
H A Ddpu_8_1_sm8450.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
36 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_0_sm8150.h29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
H A Ddpu_6_4_sm6350.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_6_2_sc7180.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_8_0_sc8280xp.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_1_sc8180x.h29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
H A Ddpu_7_2_sc7280.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_5_4_sm6125.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
H A Ddpu_6_5_qcm2290.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
H A Ddpu_6_3_sm6115.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
H A Ddpu_6_9_sm6375.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
/openbmc/linux/fs/ocfs2/
H A Dlocalalloc.h39 u32 *bit_off,
45 u32 bit_off,
H A Dlocalalloc.c717 u32 *bit_off, in ocfs2_claim_local_alloc_bits() argument
742 *bit_off = le32_to_cpu(la->la_bm_off) + start; in ocfs2_claim_local_alloc_bits()
772 u32 bit_off, in ocfs2_free_local_alloc_bits() argument
789 start = bit_off - le32_to_cpu(la->la_bm_off); in ocfs2_free_local_alloc_bits()
954 int bit_off, left, count, start; in ocfs2_sync_local_to_main() local
979 while ((bit_off = ocfs2_find_next_zero_bit(bitmap, left, start)) in ocfs2_sync_local_to_main()
981 if ((bit_off < left) && (bit_off == start)) { in ocfs2_sync_local_to_main()
1005 if (bit_off >= left) in ocfs2_sync_local_to_main()
1008 start = bit_off + 1; in ocfs2_sync_local_to_main()
/openbmc/linux/tools/testing/selftests/bpf/
H A Dbtf_helpers.c130 __u32 bit_off, bit_sz; in fprintf_btf_type_raw() local
132 bit_off = btf_member_bit_offset(t, i); in fprintf_btf_type_raw()
135 btf_str(btf, m->name_off), m->type, bit_off); in fprintf_btf_type_raw()
/openbmc/linux/drivers/thermal/samsung/
H A Dexynos_tmu.c515 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_temp() local
519 bit_off = ((8 - trip) % 2); in exynos7_tmu_set_trip_temp()
522 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); in exynos7_tmu_set_trip_temp()
523 th |= temp_to_code(data, temp) << (16 * bit_off); in exynos7_tmu_set_trip_temp()
530 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_hyst() local
534 bit_off = ((8 - trip) % 2); in exynos7_tmu_set_trip_hyst()
537 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); in exynos7_tmu_set_trip_hyst()
538 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); in exynos7_tmu_set_trip_hyst()

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