197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
325fdd593SJeykumar Sankaran */
425fdd593SJeykumar Sankaran
525fdd593SJeykumar Sankaran #include "dpu_hwio.h"
625fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h"
725fdd593SJeykumar Sankaran #include "dpu_hw_top.h"
825fdd593SJeykumar Sankaran #include "dpu_kms.h"
925fdd593SJeykumar Sankaran
1025fdd593SJeykumar Sankaran #define FLD_SPLIT_DISPLAY_CMD BIT(1)
1125fdd593SJeykumar Sankaran #define FLD_SMART_PANEL_FREE_RUN BIT(2)
1225fdd593SJeykumar Sankaran #define FLD_INTF_1_SW_TRG_MUX BIT(4)
1325fdd593SJeykumar Sankaran #define FLD_INTF_2_SW_TRG_MUX BIT(8)
1425fdd593SJeykumar Sankaran #define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
1525fdd593SJeykumar Sankaran
1625fdd593SJeykumar Sankaran #define TRAFFIC_SHAPER_EN BIT(31)
1725fdd593SJeykumar Sankaran #define TRAFFIC_SHAPER_RD_CLIENT(num) (0x030 + (num * 4))
1825fdd593SJeykumar Sankaran #define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4))
1925fdd593SJeykumar Sankaran #define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4
2025fdd593SJeykumar Sankaran
2125fdd593SJeykumar Sankaran #define MDP_TICK_COUNT 16
2225fdd593SJeykumar Sankaran #define XO_CLK_RATE 19200
2325fdd593SJeykumar Sankaran #define MS_TICKS_IN_SEC 1000
2425fdd593SJeykumar Sankaran
2525fdd593SJeykumar Sankaran #define CALCULATE_WD_LOAD_VALUE(fps) \
2625fdd593SJeykumar Sankaran ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
2725fdd593SJeykumar Sankaran
dpu_hw_setup_split_pipe(struct dpu_hw_mdp * mdp,struct split_pipe_cfg * cfg)2825fdd593SJeykumar Sankaran static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
2925fdd593SJeykumar Sankaran struct split_pipe_cfg *cfg)
3025fdd593SJeykumar Sankaran {
3125fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
3225fdd593SJeykumar Sankaran u32 upper_pipe = 0;
3325fdd593SJeykumar Sankaran u32 lower_pipe = 0;
3425fdd593SJeykumar Sankaran
3525fdd593SJeykumar Sankaran if (!mdp || !cfg)
3625fdd593SJeykumar Sankaran return;
3725fdd593SJeykumar Sankaran
3825fdd593SJeykumar Sankaran c = &mdp->hw;
3925fdd593SJeykumar Sankaran
4025fdd593SJeykumar Sankaran if (cfg->en) {
4125fdd593SJeykumar Sankaran if (cfg->mode == INTF_MODE_CMD) {
4225fdd593SJeykumar Sankaran lower_pipe = FLD_SPLIT_DISPLAY_CMD;
4325fdd593SJeykumar Sankaran /* interface controlling sw trigger */
4425fdd593SJeykumar Sankaran if (cfg->intf == INTF_2)
4525fdd593SJeykumar Sankaran lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
4625fdd593SJeykumar Sankaran else
4725fdd593SJeykumar Sankaran lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
4825fdd593SJeykumar Sankaran upper_pipe = lower_pipe;
4925fdd593SJeykumar Sankaran } else {
5025fdd593SJeykumar Sankaran if (cfg->intf == INTF_2) {
5125fdd593SJeykumar Sankaran lower_pipe = FLD_INTF_1_SW_TRG_MUX;
5225fdd593SJeykumar Sankaran upper_pipe = FLD_INTF_2_SW_TRG_MUX;
5325fdd593SJeykumar Sankaran } else {
5425fdd593SJeykumar Sankaran lower_pipe = FLD_INTF_2_SW_TRG_MUX;
5525fdd593SJeykumar Sankaran upper_pipe = FLD_INTF_1_SW_TRG_MUX;
5625fdd593SJeykumar Sankaran }
5725fdd593SJeykumar Sankaran }
5825fdd593SJeykumar Sankaran }
5925fdd593SJeykumar Sankaran
6025fdd593SJeykumar Sankaran DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
6125fdd593SJeykumar Sankaran DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
6225fdd593SJeykumar Sankaran DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
6325fdd593SJeykumar Sankaran DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
6425fdd593SJeykumar Sankaran }
6525fdd593SJeykumar Sankaran
dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp * mdp,enum dpu_clk_ctrl_type clk_ctrl,bool enable)6625fdd593SJeykumar Sankaran static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
6725fdd593SJeykumar Sankaran enum dpu_clk_ctrl_type clk_ctrl, bool enable)
6825fdd593SJeykumar Sankaran {
6925fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
7025fdd593SJeykumar Sankaran u32 reg_off, bit_off;
7125fdd593SJeykumar Sankaran u32 reg_val, new_val;
7225fdd593SJeykumar Sankaran bool clk_forced_on;
7325fdd593SJeykumar Sankaran
7425fdd593SJeykumar Sankaran if (!mdp)
7525fdd593SJeykumar Sankaran return false;
7625fdd593SJeykumar Sankaran
7725fdd593SJeykumar Sankaran c = &mdp->hw;
7825fdd593SJeykumar Sankaran
7925fdd593SJeykumar Sankaran if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
8025fdd593SJeykumar Sankaran return false;
8125fdd593SJeykumar Sankaran
8225fdd593SJeykumar Sankaran reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
8325fdd593SJeykumar Sankaran bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
8425fdd593SJeykumar Sankaran
8525fdd593SJeykumar Sankaran reg_val = DPU_REG_READ(c, reg_off);
8625fdd593SJeykumar Sankaran
8725fdd593SJeykumar Sankaran if (enable)
8825fdd593SJeykumar Sankaran new_val = reg_val | BIT(bit_off);
8925fdd593SJeykumar Sankaran else
9025fdd593SJeykumar Sankaran new_val = reg_val & ~BIT(bit_off);
9125fdd593SJeykumar Sankaran
9225fdd593SJeykumar Sankaran DPU_REG_WRITE(c, reg_off, new_val);
9325fdd593SJeykumar Sankaran
9425fdd593SJeykumar Sankaran clk_forced_on = !(reg_val & BIT(bit_off));
9525fdd593SJeykumar Sankaran
9625fdd593SJeykumar Sankaran return clk_forced_on;
9725fdd593SJeykumar Sankaran }
9825fdd593SJeykumar Sankaran
9925fdd593SJeykumar Sankaran
dpu_hw_get_danger_status(struct dpu_hw_mdp * mdp,struct dpu_danger_safe_status * status)10025fdd593SJeykumar Sankaran static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp,
10125fdd593SJeykumar Sankaran struct dpu_danger_safe_status *status)
10225fdd593SJeykumar Sankaran {
10325fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
10425fdd593SJeykumar Sankaran u32 value;
10525fdd593SJeykumar Sankaran
10625fdd593SJeykumar Sankaran if (!mdp || !status)
10725fdd593SJeykumar Sankaran return;
10825fdd593SJeykumar Sankaran
10925fdd593SJeykumar Sankaran c = &mdp->hw;
11025fdd593SJeykumar Sankaran
11125fdd593SJeykumar Sankaran value = DPU_REG_READ(c, DANGER_STATUS);
11225fdd593SJeykumar Sankaran status->mdp = (value >> 0) & 0x3;
11325fdd593SJeykumar Sankaran status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
11425fdd593SJeykumar Sankaran status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
11525fdd593SJeykumar Sankaran status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
11625fdd593SJeykumar Sankaran status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
11725fdd593SJeykumar Sankaran status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
11825fdd593SJeykumar Sankaran status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
11925fdd593SJeykumar Sankaran status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
12025fdd593SJeykumar Sankaran status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
12125fdd593SJeykumar Sankaran status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
12225fdd593SJeykumar Sankaran status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
12325fdd593SJeykumar Sankaran status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
12425fdd593SJeykumar Sankaran status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
12525fdd593SJeykumar Sankaran status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
12625fdd593SJeykumar Sankaran status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
12725fdd593SJeykumar Sankaran }
12825fdd593SJeykumar Sankaran
dpu_hw_setup_vsync_source(struct dpu_hw_mdp * mdp,struct dpu_vsync_source_cfg * cfg)12925fdd593SJeykumar Sankaran static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
13025fdd593SJeykumar Sankaran struct dpu_vsync_source_cfg *cfg)
13125fdd593SJeykumar Sankaran {
13225fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
133a2ff0968SMarijn Suijten u32 reg, wd_load_value, wd_ctl, wd_ctl2;
13425fdd593SJeykumar Sankaran
135a2ff0968SMarijn Suijten if (!mdp || !cfg)
13625fdd593SJeykumar Sankaran return;
13725fdd593SJeykumar Sankaran
13825fdd593SJeykumar Sankaran c = &mdp->hw;
13925fdd593SJeykumar Sankaran
14025fdd593SJeykumar Sankaran if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
14125fdd593SJeykumar Sankaran cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) {
14225fdd593SJeykumar Sankaran switch (cfg->vsync_source) {
14325fdd593SJeykumar Sankaran case DPU_VSYNC_SOURCE_WD_TIMER_4:
14425fdd593SJeykumar Sankaran wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE;
14525fdd593SJeykumar Sankaran wd_ctl = MDP_WD_TIMER_4_CTL;
14625fdd593SJeykumar Sankaran wd_ctl2 = MDP_WD_TIMER_4_CTL2;
14725fdd593SJeykumar Sankaran break;
14825fdd593SJeykumar Sankaran case DPU_VSYNC_SOURCE_WD_TIMER_3:
14925fdd593SJeykumar Sankaran wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE;
15025fdd593SJeykumar Sankaran wd_ctl = MDP_WD_TIMER_3_CTL;
15125fdd593SJeykumar Sankaran wd_ctl2 = MDP_WD_TIMER_3_CTL2;
15225fdd593SJeykumar Sankaran break;
15325fdd593SJeykumar Sankaran case DPU_VSYNC_SOURCE_WD_TIMER_2:
15425fdd593SJeykumar Sankaran wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE;
15525fdd593SJeykumar Sankaran wd_ctl = MDP_WD_TIMER_2_CTL;
15625fdd593SJeykumar Sankaran wd_ctl2 = MDP_WD_TIMER_2_CTL2;
15725fdd593SJeykumar Sankaran break;
15825fdd593SJeykumar Sankaran case DPU_VSYNC_SOURCE_WD_TIMER_1:
15925fdd593SJeykumar Sankaran wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE;
16025fdd593SJeykumar Sankaran wd_ctl = MDP_WD_TIMER_1_CTL;
16125fdd593SJeykumar Sankaran wd_ctl2 = MDP_WD_TIMER_1_CTL2;
16225fdd593SJeykumar Sankaran break;
16325fdd593SJeykumar Sankaran case DPU_VSYNC_SOURCE_WD_TIMER_0:
16425fdd593SJeykumar Sankaran default:
16525fdd593SJeykumar Sankaran wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE;
16625fdd593SJeykumar Sankaran wd_ctl = MDP_WD_TIMER_0_CTL;
16725fdd593SJeykumar Sankaran wd_ctl2 = MDP_WD_TIMER_0_CTL2;
16825fdd593SJeykumar Sankaran break;
16925fdd593SJeykumar Sankaran }
17025fdd593SJeykumar Sankaran
17125fdd593SJeykumar Sankaran DPU_REG_WRITE(c, wd_load_value,
17225fdd593SJeykumar Sankaran CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
17325fdd593SJeykumar Sankaran
17425fdd593SJeykumar Sankaran DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */
17525fdd593SJeykumar Sankaran reg = DPU_REG_READ(c, wd_ctl2);
17625fdd593SJeykumar Sankaran reg |= BIT(8); /* enable heartbeat timer */
17725fdd593SJeykumar Sankaran reg |= BIT(0); /* enable WD timer */
17825fdd593SJeykumar Sankaran DPU_REG_WRITE(c, wd_ctl2, reg);
17925fdd593SJeykumar Sankaran
18025fdd593SJeykumar Sankaran /* make sure that timers are enabled/disabled for vsync state */
18125fdd593SJeykumar Sankaran wmb();
18225fdd593SJeykumar Sankaran }
18325fdd593SJeykumar Sankaran }
18425fdd593SJeykumar Sankaran
dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp * mdp,struct dpu_vsync_source_cfg * cfg)185a2ff0968SMarijn Suijten static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp,
186a2ff0968SMarijn Suijten struct dpu_vsync_source_cfg *cfg)
187a2ff0968SMarijn Suijten {
188a2ff0968SMarijn Suijten struct dpu_hw_blk_reg_map *c;
189a2ff0968SMarijn Suijten u32 reg, i;
190a2ff0968SMarijn Suijten static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};
191a2ff0968SMarijn Suijten
192a2ff0968SMarijn Suijten if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
193a2ff0968SMarijn Suijten return;
194a2ff0968SMarijn Suijten
195a2ff0968SMarijn Suijten c = &mdp->hw;
196a2ff0968SMarijn Suijten
197a2ff0968SMarijn Suijten reg = DPU_REG_READ(c, MDP_VSYNC_SEL);
198a2ff0968SMarijn Suijten for (i = 0; i < cfg->pp_count; i++) {
199a2ff0968SMarijn Suijten int pp_idx = cfg->ppnumber[i] - PINGPONG_0;
200a2ff0968SMarijn Suijten
201a2ff0968SMarijn Suijten if (pp_idx >= ARRAY_SIZE(pp_offset))
202a2ff0968SMarijn Suijten continue;
203a2ff0968SMarijn Suijten
204a2ff0968SMarijn Suijten reg &= ~(0xf << pp_offset[pp_idx]);
205a2ff0968SMarijn Suijten reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
206a2ff0968SMarijn Suijten }
207a2ff0968SMarijn Suijten DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);
208a2ff0968SMarijn Suijten
209a2ff0968SMarijn Suijten dpu_hw_setup_vsync_source(mdp, cfg);
210a2ff0968SMarijn Suijten }
211a2ff0968SMarijn Suijten
dpu_hw_get_safe_status(struct dpu_hw_mdp * mdp,struct dpu_danger_safe_status * status)21225fdd593SJeykumar Sankaran static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
21325fdd593SJeykumar Sankaran struct dpu_danger_safe_status *status)
21425fdd593SJeykumar Sankaran {
21525fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
21625fdd593SJeykumar Sankaran u32 value;
21725fdd593SJeykumar Sankaran
21825fdd593SJeykumar Sankaran if (!mdp || !status)
21925fdd593SJeykumar Sankaran return;
22025fdd593SJeykumar Sankaran
22125fdd593SJeykumar Sankaran c = &mdp->hw;
22225fdd593SJeykumar Sankaran
22325fdd593SJeykumar Sankaran value = DPU_REG_READ(c, SAFE_STATUS);
22425fdd593SJeykumar Sankaran status->mdp = (value >> 0) & 0x1;
22525fdd593SJeykumar Sankaran status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
22625fdd593SJeykumar Sankaran status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
22725fdd593SJeykumar Sankaran status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
22825fdd593SJeykumar Sankaran status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
22925fdd593SJeykumar Sankaran status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
23025fdd593SJeykumar Sankaran status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
23125fdd593SJeykumar Sankaran status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
23225fdd593SJeykumar Sankaran status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
23325fdd593SJeykumar Sankaran status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
23425fdd593SJeykumar Sankaran status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
23525fdd593SJeykumar Sankaran status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
23625fdd593SJeykumar Sankaran status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
23725fdd593SJeykumar Sankaran status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
23825fdd593SJeykumar Sankaran status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
23925fdd593SJeykumar Sankaran }
24025fdd593SJeykumar Sankaran
dpu_hw_intf_audio_select(struct dpu_hw_mdp * mdp)24125fdd593SJeykumar Sankaran static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
24225fdd593SJeykumar Sankaran {
24325fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map *c;
24425fdd593SJeykumar Sankaran
24525fdd593SJeykumar Sankaran if (!mdp)
24625fdd593SJeykumar Sankaran return;
24725fdd593SJeykumar Sankaran
24825fdd593SJeykumar Sankaran c = &mdp->hw;
24925fdd593SJeykumar Sankaran
25025fdd593SJeykumar Sankaran DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
25125fdd593SJeykumar Sankaran }
25225fdd593SJeykumar Sankaran
_setup_mdp_ops(struct dpu_hw_mdp_ops * ops,unsigned long cap)25325fdd593SJeykumar Sankaran static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
25425fdd593SJeykumar Sankaran unsigned long cap)
25525fdd593SJeykumar Sankaran {
25625fdd593SJeykumar Sankaran ops->setup_split_pipe = dpu_hw_setup_split_pipe;
25725fdd593SJeykumar Sankaran ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
25825fdd593SJeykumar Sankaran ops->get_danger_status = dpu_hw_get_danger_status;
259a2ff0968SMarijn Suijten
260a2ff0968SMarijn Suijten if (cap & BIT(DPU_MDP_VSYNC_SEL))
261a2ff0968SMarijn Suijten ops->setup_vsync_source = dpu_hw_setup_vsync_source_and_vsync_sel;
262a2ff0968SMarijn Suijten else
26325fdd593SJeykumar Sankaran ops->setup_vsync_source = dpu_hw_setup_vsync_source;
264a2ff0968SMarijn Suijten
26525fdd593SJeykumar Sankaran ops->get_safe_status = dpu_hw_get_safe_status;
26603490e11SKuogee Hsieh
26703490e11SKuogee Hsieh if (cap & BIT(DPU_MDP_AUDIO_SELECT))
26825fdd593SJeykumar Sankaran ops->intf_audio_select = dpu_hw_intf_audio_select;
26925fdd593SJeykumar Sankaran }
27025fdd593SJeykumar Sankaran
dpu_hw_mdptop_init(const struct dpu_mdp_cfg * cfg,void __iomem * addr,const struct dpu_mdss_cfg * m)271*6b2dc8cfSDmitry Baryshkov struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
27225fdd593SJeykumar Sankaran void __iomem *addr,
27325fdd593SJeykumar Sankaran const struct dpu_mdss_cfg *m)
27425fdd593SJeykumar Sankaran {
27525fdd593SJeykumar Sankaran struct dpu_hw_mdp *mdp;
27625fdd593SJeykumar Sankaran
277*6b2dc8cfSDmitry Baryshkov if (!addr)
27825fdd593SJeykumar Sankaran return ERR_PTR(-EINVAL);
27925fdd593SJeykumar Sankaran
28025fdd593SJeykumar Sankaran mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
28125fdd593SJeykumar Sankaran if (!mdp)
28225fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM);
28325fdd593SJeykumar Sankaran
284*6b2dc8cfSDmitry Baryshkov mdp->hw.blk_addr = addr + cfg->base;
285*6b2dc8cfSDmitry Baryshkov mdp->hw.log_mask = DPU_DBG_MASK_TOP;
28625fdd593SJeykumar Sankaran
28725fdd593SJeykumar Sankaran /*
28825fdd593SJeykumar Sankaran * Assign ops
28925fdd593SJeykumar Sankaran */
29025fdd593SJeykumar Sankaran mdp->caps = cfg;
29125fdd593SJeykumar Sankaran _setup_mdp_ops(&mdp->ops, mdp->caps->features);
29225fdd593SJeykumar Sankaran
29325fdd593SJeykumar Sankaran return mdp;
29425fdd593SJeykumar Sankaran }
29525fdd593SJeykumar Sankaran
dpu_hw_mdp_destroy(struct dpu_hw_mdp * mdp)29625fdd593SJeykumar Sankaran void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
29725fdd593SJeykumar Sankaran {
29825fdd593SJeykumar Sankaran kfree(mdp);
29925fdd593SJeykumar Sankaran }
30025fdd593SJeykumar Sankaran
301