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/openbmc/u-boot/tools/
H A Dvybridimage.c42 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc() local
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h10 uint8_t bit0 : 1; member
37 uint8_t bit0 : 1; member
59 uint8_t bit0 : 1; member
97 uint8_t bit0 : 1; member
/openbmc/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
71 - cp4 is the parity over bit0, bit1, bit2 and bit3.
160 cp0 = bit6 ^ bit4 ^ bit2 ^ bit0 ^ cp0;
162 cp2 = bit5 ^ bit4 ^ bit1 ^ bit0 ^ cp2;
[all …]
/openbmc/linux/include/uapi/linux/
H A Dioam6.h62 bit0:1, member
97 __u32 bit0:1, member
/openbmc/linux/Documentation/leds/
H A Dleds-mlxcpld.rst53 [bit3,bit2,bit1,bit0] or
98 [bit3,bit2,bit1,bit0] or
110 [bit3,bit2,bit1,bit0]:
/openbmc/qemu/target/i386/hvf/
H A Dx86_emu.c1111 uint32_t bit0, bit7; in exec_rol() local
1118 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
1129 bit0 = (res & 1); in exec_rol()
1131 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
1137 uint32_t bit0, bit15; in exec_rol() local
1145 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
1153 bit0 = (res & 0x1); in exec_rol()
1156 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
1162 uint32_t bit0, bit31; in exec_rol() local
1171 bit0 = (res & 0x1); in exec_rol()
[all …]
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
145 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 1, Window enabled
142 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 1, Window enabled
144 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/linux/drivers/input/touchscreen/
H A Dwdt87xx_i2c.c611 u32 bit0; in misr() local
616 bit0 = a ^ (b & 1); in misr()
617 bit0 ^= a >> 1; in misr()
618 bit0 ^= a >> 2; in misr()
619 bit0 ^= a >> 4; in misr()
620 bit0 ^= a >> 5; in misr()
621 bit0 ^= a >> 7; in misr()
622 bit0 ^= a >> 11; in misr()
623 bit0 ^= a >> 15; in misr()
625 y = (y & ~1) | (bit0 & 1); in misr()
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-ns2l.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-is2.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg96 # bit0: 0, OpenPage enabled
105 # bit0: 0, DDR DLL enabled
132 # bit0: 1, Window enabled
158 # bit0=1, enable DDR init upon this register write
H A Dkwbimage-memphis.cfg99 # bit0: 0, OpenPage enabled
108 # bit0: 0, DDR DLL enabled
147 # bit0: 1, Window enabled
176 # bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
150 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 0x1, Window enabled
147 # bit0: 0x1, enable DDR init upon this register write
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 0x1, Window enabled
146 # bit0: 0x1, enable DDR init upon this register write
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg85 # bit0: 0, OPEn=OpenPage enabled
103 # bit0: 0, DRAM DLL enabled
143 # bit0: 1, Window enabled
151 # bit0: 1, Window enabled
186 # bit0: 1, enable DDR init upon this register write

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