| /openbmc/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/ |
| H A D | pearl_pcie_regs.h | 8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
21 #define PCIE_HDP_INT_EN(base) ((base) + 0x2c3c) argument
35 #define PCIE_HDP_CFG0(base) ((base) + 0x2c80) argument
36 #define PCIE_HDP_CFG1(base) ((base) + 0x2c84) argument
37 #define PCIE_HDP_CFG2(base) ((base) + 0x2c88) argument
38 #define PCIE_HDP_CFG3(base) ((base) + 0x2c8c) argument
39 #define PCIE_HDP_CFG4(base) ((base) + 0x2c90) argument
47 #define PCIE_INT(base) ((base) + 0x2cb0) argument
[all …]
|
| H A D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
24 #define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C) argument
25 #define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140) argument
34 #define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C) argument
[all …]
|
| /openbmc/u-boot/board/micronas/vct/vcth2/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
40 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
48 #define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) argument
50 #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) argument
60 #define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) argument
62 #define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) argument
64 #define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) argument
[all …]
|
| /openbmc/u-boot/board/micronas/vct/vctv/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
40 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
48 #define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) argument
50 #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) argument
60 #define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) argument
62 #define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) argument
64 #define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) argument
[all …]
|
| /openbmc/u-boot/board/micronas/vct/vcth/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
38 #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) argument
[all …]
|
| H A D | reg_fwsram.h | 21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
53 #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) argument
55 #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) argument
[all …]
|
| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_regs.h | 11 #define RING_EXCC(base) _MMIO((base) + 0x28) argument
12 #define RING_TAIL(base) _MMIO((base) + 0x30) argument
14 #define RING_HEAD(base) _MMIO((base) + 0x34) argument
18 #define RING_START(base) _MMIO((base) + 0x38) argument
19 #define RING_CTL(base) _MMIO((base) + 0x3c) argument
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40) argument
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44) argument
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48) argument
68 #define IPEIR(base) _MMIO((base) + 0x88) argument
69 #define IPEHR(base) _MMIO((base) + 0x8c) argument
[all …]
|
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx7d.c | 383 void __iomem *base; in imx7d_clocks_init() local
398 base = of_iomap(np, 0); in imx7d_clocks_init()
399 WARN_ON(!base); in imx7d_clocks_init()
489 base = of_iomap(np, 0); in imx7d_clocks_init()
490 WARN_ON(!base); in imx7d_clocks_init()
572 hws[IMX7D_DRAM_ROOT_CG] = imx_clk_hw_gate3("dram_cg", "dram_src", base + 0x9880, 28); in imx7d_clocks_init()
583 hws[IMX7D_SAI1_ROOT_CG] = imx_clk_hw_gate3("sai1_cg", "sai1_src", base + 0xa500, 28); in imx7d_clocks_init()
584 hws[IMX7D_SAI2_ROOT_CG] = imx_clk_hw_gate3("sai2_cg", "sai2_src", base + 0xa580, 28); in imx7d_clocks_init()
585 hws[IMX7D_SAI3_ROOT_CG] = imx_clk_hw_gate3("sai3_cg", "sai3_src", base + 0xa600, 28); in imx7d_clocks_init()
592 hws[IMX7D_EIM_ROOT_CG] = imx_clk_hw_gate3("eim_cg", "eim_src", base + 0xa980, 28); in imx7d_clocks_init()
[all …]
|
| H A D | clk-imx8ulp.c | 53 void __iomem *base; member
134 pcc_reset->base = base; in imx8ulp_pcc_reset_init()
150 void __iomem *base; in imx8ulp_clk_cgc1_init() local
165 return PTR_ERR(base); in imx8ulp_clk_cgc1_init()
234 void __iomem *base; in imx8ulp_clk_cgc2_init() local
247 return PTR_ERR(base); in imx8ulp_clk_cgc2_init()
316 void __iomem *base; in imx8ulp_clk_pcc3_init() local
330 return PTR_ERR(base); in imx8ulp_clk_pcc3_init()
399 void __iomem *base; in imx8ulp_clk_pcc4_init() local
413 return PTR_ERR(base); in imx8ulp_clk_pcc4_init()
[all …]
|
| H A D | clk-imx6sll.c | 82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
191 base = of_iomap(np, 0); in imx6sll_clocks_init()
192 WARN_ON(!base); in imx6sll_clocks_init()
218 …hws[IMX6SLL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, peri… in imx6sll_clocks_init()
244 …hws[IMX6SLL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48… in imx6sll_clocks_init()
245 …K_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, … in imx6sll_clocks_init()
246 …hws[IMX6SLL_CLK_AXI_PODF] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base +… in imx6sll_clocks_init()
247 …hws[IMX6SLL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48… in imx6sll_clocks_init()
[all …]
|
| H A D | clk-imx6sl.c | 185 void __iomem *base; in imx6sl_clocks_init() local
203 base = of_iomap(np, 0); in imx6sl_clocks_init()
204 WARN_ON(!base); in imx6sl_clocks_init()
206 anatop_base = base; in imx6sl_clocks_init()
289 base = of_iomap(np, 0); in imx6sl_clocks_init()
290 WARN_ON(!base); in imx6sl_clocks_init()
291 ccm_base = base; in imx6sl_clocks_init()
364 …K_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48,… in imx6sl_clocks_init()
365 …K_MMDC_ROOT] = imx_clk_hw_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48,… in imx6sl_clocks_init()
366 …K_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48,… in imx6sl_clocks_init()
[all …]
|
| H A D | clk-imx6ul.c | 131 void __iomem *base; in imx6ul_clocks_init() local
151 base = of_iomap(np, 0); in imx6ul_clocks_init()
153 WARN_ON(!base); in imx6ul_clocks_init()
248 base = of_iomap(np, 0); in imx6ul_clocks_init()
249 WARN_ON(!base); in imx6ul_clocks_init()
301 …hws[IMX6UL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, perip… in imx6ul_clocks_init()
342 …hws[IMX6UL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0… in imx6ul_clocks_init()
343 …K_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, … in imx6ul_clocks_init()
344 …LK_AXI_PODF] = imx_clk_hw_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, … in imx6ul_clocks_init()
345 …hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0… in imx6ul_clocks_init()
[all …]
|
| H A D | clk-imx6sx.c | 123 void __iomem *base; in imx6sx_clocks_init() local
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
148 WARN_ON(!base); in imx6sx_clocks_init()
219 base + 0xe0, 0, 2, 0, clk_enet_ref_table, in imx6sx_clocks_init()
222 base + 0xe0, 2, 2, 0, clk_enet_ref_table, in imx6sx_clocks_init()
261 base = of_iomap(np, 0); in imx6sx_clocks_init()
262 WARN_ON(!base); in imx6sx_clocks_init()
363 …] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48… in imx6sx_clocks_init()
364 … = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48… in imx6sx_clocks_init()
365 … = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48… in imx6sx_clocks_init()
[all …]
|
| H A D | clk-imx8mq.c | 288 void __iomem *base; in imx8mq_clocks_probe() local
308 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
310 if (WARN_ON(IS_ERR(base))) { in imx8mq_clocks_probe()
311 err = PTR_ERR(base); in imx8mq_clocks_probe()
332 hws[IMX8MQ_ARM_PLL] = imx_clk_hw_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); in imx8mq_clocks_probe()
333 hws[IMX8MQ_GPU_PLL] = imx_clk_hw_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); in imx8mq_clocks_probe()
334 hws[IMX8MQ_VPU_PLL] = imx_clk_hw_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); in imx8mq_clocks_probe()
398 base = devm_platform_ioremap_resource(pdev, 0); in imx8mq_clocks_probe()
399 if (WARN_ON(IS_ERR(base))) { in imx8mq_clocks_probe()
400 err = PTR_ERR(base); in imx8mq_clocks_probe()
[all …]
|
| H A D | clk-imx8mm.c | 303 void __iomem *base; in imx8mm_clocks_probe() local
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
325 if (WARN_ON(!base)) in imx8mm_clocks_probe()
395 hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); in imx8mm_clocks_probe()
398 hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); in imx8mm_clocks_probe()
401 base = devm_platform_ioremap_resource(pdev, 0); in imx8mm_clocks_probe()
402 if (WARN_ON(IS_ERR(base))) in imx8mm_clocks_probe()
403 return PTR_ERR(base); in imx8mm_clocks_probe()
451 hws[IMX8MM_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); in imx8mm_clocks_probe()
472 hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); in imx8mm_clocks_probe()
[all …]
|
| H A D | clk-imx8mn.c | 323 void __iomem *base; in imx8mn_clocks_probe() local
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
345 if (WARN_ON(IS_ERR(base))) { in imx8mn_clocks_probe()
346 ret = PTR_ERR(base); in imx8mn_clocks_probe()
416 hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); in imx8mn_clocks_probe()
419 hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); in imx8mn_clocks_probe()
422 base = devm_platform_ioremap_resource(pdev, 0); in imx8mn_clocks_probe()
423 if (WARN_ON(IS_ERR(base))) { in imx8mn_clocks_probe()
424 ret = PTR_ERR(base); in imx8mn_clocks_probe()
461 hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); in imx8mn_clocks_probe()
[all …]
|
| H A D | clk-imx6q.c | 439 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
461 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
462 WARN_ON(!base); in imx6q_clocks_init()
546 base + 0xe0, 0, 2, 0, clk_enet_ref_table, in imx6q_clocks_init()
569 writel(readl(base + 0x160) & ~0x3c00, base + 0x160); in imx6q_clocks_init()
607 base = of_iomap(np, 0); in imx6q_clocks_init()
608 WARN_ON(!base); in imx6q_clocks_init()
646 imx_mmdc_mask_handshake(base, 1); in imx6q_clocks_init()
657 init_ldb_clks(np, base); in imx6q_clocks_init()
783 … = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48,… in imx6q_clocks_init()
[all …]
|
| /openbmc/qemu/hw/m68k/ |
| H A D | bootinfo.h | 18 base += 2; \
20 base += 2; \
26 base += 2; \
28 base += 2; \
30 base += 4; \
36 base += 2; \
38 base += 2; \
40 base += 4; \
42 base += 4; \
57 base = QEMU_ALIGN_PTR_UP(base, 4); \
[all …]
|
| /openbmc/linux/drivers/gpu/drm/sun4i/ |
| H A D | sun8i_vi_scaler.h | 30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
40 #define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90) argument
41 #define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98) argument
42 #define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0) argument
43 #define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8) argument
[all …]
|
| /openbmc/linux/drivers/scsi/ |
| H A D | aha1740.h | 19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
26 #define INTDEF(base) (base + 0x42) argument
28 #define BUSDEF(base) (base + 0x44) argument
29 #define RESV0(base) (base + 0x45) argument
30 #define RESV1(base) (base + 0x46) argument
[all …]
|
| H A D | nsp32_io.h | 16 outb(val, (base + index)); in nsp32_write1()
22 return inb(base + index); in nsp32_read1()
29 outw(val, (base + index)); in nsp32_write2()
35 return inw(base + index); in nsp32_read2()
42 outl(val, (base + index)); in nsp32_write4()
48 return inl(base + index); in nsp32_read4()
121 outb(reg, base + INDEX_REG); in nsp32_index_read1()
136 outb(reg, base + INDEX_REG); in nsp32_index_read2()
153 outb(reg, base + INDEX_REG); in nsp32_index_read4()
154 l = inw(base + DATA_REG_LOW); in nsp32_index_read4()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | hdmi5_core.c | 28 void __iomem *base = core->base; in hdmi5_core_ddc_init() local
107 void __iomem *base = core->base; in hdmi5_core_ddc_uninit() local
118 void __iomem *base = core->base; in hdmi5_core_ddc_read() local
275 void __iomem *base = core->base; in hdmi_core_video_config() local
337 void __iomem *base = core->base; in hdmi_core_config_video_packetizer() local
367 void __iomem *base = core->base; in hdmi_core_write_avi_infoframe() local
423 void __iomem *base = core->base; in hdmi_core_write_csc() local
485 void __iomem *base = core->base; in hdmi_core_enable_video_path() local
501 void __iomem *base = core->base; in hdmi_core_mask_interrupts() local
550 void __iomem *base = core->base; in hdmi5_core_handle_irqs() local
[all …]
|
| /openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | hdmi5_core.c | 41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
120 void __iomem *base = core->base; in hdmi_core_ddc_uninit() local
130 void __iomem *base = core->base; in hdmi_core_ddc_edid() local
307 void __iomem *base = core->base; in hdmi_core_video_config() local
371 void __iomem *base = core->base; in hdmi_core_config_video_packetizer() local
409 void __iomem *base = core->base; in hdmi_core_write_avi_infoframe() local
465 void __iomem *base = core->base; in hdmi_core_csc_config() local
507 void __iomem *base = core->base; in hdmi_core_enable_video_path() local
523 void __iomem *base = core->base; in hdmi_core_mask_interrupts() local
572 void __iomem *base = core->base; in hdmi5_core_handle_irqs() local
[all …]
|
| /openbmc/linux/arch/loongarch/kernel/ |
| H A D | fpu.S | 28 .macro sc_save_fp base argument
63 .macro sc_restore_fp base argument
115 EX st.d \tmp1, \base, 0
119 EX ld.d \tmp0, \base, 0
138 .macro sc_save_fcsr base, tmp0
140 EX st.w \tmp0, \base, 0
151 EX ld.w \tmp0, \base, 0
155 .macro sc_save_lsx base argument
192 .macro sc_restore_lsx base argument
229 .macro sc_save_lasx base argument
[all …]
|
| /openbmc/linux/arch/mips/alchemy/common/ |
| H A D | usb.c | 159 __au1300_usb_phyctl(base, enable); in __au1300_ohci_control()
267 void __iomem *base = in au1300_usb_control() local
295 void __iomem *base = in au1300_usb_init() local
362 void __iomem *base = in au1200_usb_control() local
385 void __iomem *base = in au1200_usb_init() local
417 __raw_writel(r, base); in au1000_usb_init()
446 while (__raw_readl(base + creg), in __au1xx0_ohci_control()
519 __raw_writel(0, base + 0x04); in au1000_usb_pm()
521 __raw_writel(0, base + creg); in au1000_usb_pm()
531 void __iomem *base = in au1200_usb_pm() local
[all …]
|