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/openbmc/u-boot/board/micronas/vct/vctv/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/openbmc/u-boot/board/micronas/vct/vcth2/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/openbmc/u-boot/board/micronas/vct/vcth/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
32 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
[all …]
H A Dreg_fwsram.h21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
37 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
39 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
[all …]
H A Dreg_scc.h56 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
58 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
60 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
62 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
64 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
66 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
68 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
70 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
72 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
74 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
[all …]
/openbmc/qemu/hw/m68k/
H A Dbootinfo.h15 #define BOOTINFO0(base, id) \ argument
17 stw_be_p(base, id); \
18 base += 2; \
19 stw_be_p(base, sizeof(struct bi_record)); \
20 base += 2; \
23 #define BOOTINFO1(base, id, value) \ argument
25 stw_be_p(base, id); \
26 base += 2; \
27 stw_be_p(base, sizeof(struct bi_record) + 4); \
28 base += 2; \
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c34 void __iomem *base; in uniphier_ld20_sscpll_init() local
37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init()
38 if (!base) in uniphier_ld20_sscpll_init()
42 tmp = readl(base); /* SSCPLLCTRL */ in uniphier_ld20_sscpll_init()
47 writel(tmp, base); in uniphier_ld20_sscpll_init()
49 tmp = readl(base + 4); in uniphier_ld20_sscpll_init()
54 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
59 tmp = readl(base + 4); /* SSCPLLCTRL2 */ in uniphier_ld20_sscpll_init()
61 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
63 iounmap(base); in uniphier_ld20_sscpll_init()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy() argument
28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
[all …]
/openbmc/u-boot/drivers/net/
H A Dne2000_base.c107 u8* base; in dp83902a_init() local
114 base = dp->base; in dp83902a_init()
115 if (!base) in dp83902a_init()
123 DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ in dp83902a_init()
126 DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); in dp83902a_init()
127 DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ in dp83902a_init()
147 u8 *base = dp->base; in dp83902a_stop() local
151 DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ in dp83902a_stop()
152 DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ in dp83902a_stop()
153 DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ in dp83902a_stop()
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dmv_i2c.c68 static void i2c_reset(struct mv_i2c *base) in i2c_reset() argument
73 icr_mode = readl(&base->icr) & ICR_MODE_MASK; in i2c_reset()
74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
75 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ in i2c_reset()
77 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
81 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ in i2c_reset()
83 writel(I2C_ICR_INIT | icr_mode, &base->icr); in i2c_reset()
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ in i2c_reset()
85 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ in i2c_reset()
95 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask, in i2c_isr_set_cleared() argument
[all …]
H A Dintel_i2c.c60 u32 base; member
64 static int smbus_wait_until_ready(u32 base) in smbus_wait_until_ready() argument
71 byte = inb(base + SMBHSTSTAT); in smbus_wait_until_ready()
79 static int smbus_wait_until_done(u32 base) in smbus_wait_until_done() argument
86 byte = inb(base + SMBHSTSTAT); in smbus_wait_until_done()
94 static int smbus_block_read(u32 base, u8 dev, u8 *buffer, in smbus_block_read() argument
103 if (smbus_wait_until_ready(base) < 0) in smbus_block_read()
109 inb(base + SMBHSTCTL); in smbus_block_read()
112 outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD); in smbus_block_read()
114 outb(offset & 0xff, base + SMBHSTCMD); in smbus_block_read()
[all …]
H A Dfsl_i2c.c119 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, in set_i2c_bus_speed() argument
183 writeb(dfsr, &base->dfsrr); /* set default filter */ in set_i2c_bus_speed()
184 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
194 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
212 static int fsl_i2c_fixup(const struct fsl_i2c_base *base) in fsl_i2c_fixup() argument
227 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); in fsl_i2c_fixup()
230 while (!(readb(&base->sr) & I2C_SR_MBB)) { in fsl_i2c_fixup()
235 if (readb(&base->sr) & I2C_SR_MAL) { in fsl_i2c_fixup()
237 writeb(0, &base->cr); in fsl_i2c_fixup()
239 writeb(I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_mvebu_a3700.c12 void __iomem *base; member
36 void __iomem *base = plat->base; in mvebu_serial_putc() local
38 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) in mvebu_serial_putc()
41 writel(ch, base + UART_TX_REG); in mvebu_serial_putc()
49 void __iomem *base = plat->base; in mvebu_serial_getc() local
51 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)) in mvebu_serial_getc()
54 return readl(base + UART_RX_REG) & 0xff; in mvebu_serial_getc()
60 void __iomem *base = plat->base; in mvebu_serial_pending() local
62 if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY) in mvebu_serial_pending()
71 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
[all …]
H A Dserial_bcm6345.c85 void __iomem *base; member
90 static void bcm6345_serial_enable(void __iomem *base) in bcm6345_serial_enable() argument
92 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
97 static void bcm6345_serial_disable(void __iomem *base) in bcm6345_serial_disable() argument
99 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
104 static void bcm6345_serial_flush(void __iomem *base) in bcm6345_serial_flush() argument
107 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
111 readl(base + UART_FIFO_REG); in bcm6345_serial_flush()
114 static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) in bcm6345_serial_init() argument
119 bcm6345_serial_disable(base); in bcm6345_serial_init()
[all …]
/openbmc/qemu/tests/qtest/
H A Daspeed-hace-utils.c156 static void write_regs(QTestState *s, uint32_t base, uint64_t src, in write_regs() argument
159 qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); in write_regs()
160 qtest_writel(s, base + HACE_HASH_SRC_HI, extract64(src, 32, 32)); in write_regs()
161 qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); in write_regs()
162 qtest_writel(s, base + HACE_HASH_DIGEST_HI, extract64(out, 32, 32)); in write_regs()
163 qtest_writel(s, base + HACE_HASH_DATA_LEN, length); in write_regs()
164 qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); in write_regs()
167 void aspeed_test_md5(const char *machine, const uint32_t base, in aspeed_test_md5() argument
177 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in aspeed_test_md5()
182 write_regs(s, base, src_addr, sizeof(test_vector), in aspeed_test_md5()
[all …]
/openbmc/openbmc/poky/meta/recipes-core/packagegroups/
H A Dpackagegroup-base.bb11 packagegroup-base \
12 packagegroup-base-extended \
13 packagegroup-distro-base \
14 packagegroup-machine-base \
16 ${@bb.utils.contains("MACHINE_FEATURES", "acpi", "packagegroup-base-acpi", "",d)} \
17 ${@bb.utils.contains("MACHINE_FEATURES", "alsa", "packagegroup-base-alsa", "", d)} \
18 ${@bb.utils.contains("MACHINE_FEATURES", "ext2", "packagegroup-base-ext2", "", d)} \
19 ${@bb.utils.contains("MACHINE_FEATURES", "vfat", "packagegroup-base-vfat", "", d)} \
20 … ${@bb.utils.contains("MACHINE_FEATURES", "keyboard", "packagegroup-base-keyboard", "", d)} \
21 ${@bb.utils.contains("MACHINE_FEATURES", "pci", "packagegroup-base-pci", "",d)} \
[all …]
/openbmc/openbmc/poky/meta/recipes-core/musl/
H A Dmusl-locales_git.bb31 LICENSE:locale-base-cs-cz = "MIT"
32 LICENSE:locale-base-de-ch = "MIT"
33 LICENSE:locale-base-de-de = "MIT"
34 LICENSE:locale-base-en-gb = "MIT"
35 LICENSE:locale-base-en-us = "MIT"
36 LICENSE:locale-base-es-es = "MIT"
37 LICENSE:locale-base-fi-fi = "MIT"
38 LICENSE:locale-base-fr-ca = "MIT"
39 LICENSE:locale-base-fr-fr = "MIT"
40 LICENSE:locale-base-it-it = "MIT"
[all …]
/openbmc/u-boot/drivers/bios_emulator/
H A Dbiosemui.h67 #define readb_le(base) *((u8*)(base)) argument
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) argument
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ argument
70 ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
73 writeb_le(base + 1, (v >> 8) & 0xff)
74 #define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
75 writeb_le(base + 1, (v >> 8) & 0xff), \
76 writeb_le(base + 2, (v >> 16) & 0xff), \
[all …]
/openbmc/u-boot/lib/
H A Dlmb.c25 (unsigned long long)lmb->memory.region[i].base); in lmb_dump_all()
36 (unsigned long long)lmb->reserved.region[i].base); in lmb_dump_all()
66 phys_addr_t base1 = rgn->region[r1].base; in lmb_regions_adjacent()
68 phys_addr_t base2 = rgn->region[r2].base; in lmb_regions_adjacent()
79 rgn->region[i].base = rgn->region[i + 1].base; in lmb_remove_region()
133 void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, in lmb_init_and_reserve_range() argument
137 lmb_add(lmb, base, size); in lmb_init_and_reserve_range()
142 static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) in lmb_add_region() argument
148 rgn->region[0].base = base; in lmb_add_region()
156 phys_addr_t rgnbase = rgn->region[i].base; in lmb_add_region()
[all …]
H A Dstrto.c17 static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix() argument
19 if (*base == 0) { in _parse_integer_fixup_radix()
22 *base = 16; in _parse_integer_fixup_radix()
24 *base = 8; in _parse_integer_fixup_radix()
26 *base = 10; in _parse_integer_fixup_radix()
28 if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x') in _parse_integer_fixup_radix()
34 unsigned int base) in simple_strtoul() argument
39 cp = _parse_integer_fixup_radix(cp, &base); in simple_strtoul()
42 ? toupper(*cp) : *cp)-'A'+10) < base) { in simple_strtoul()
43 result = result*base + value; in simple_strtoul()
[all …]
/openbmc/u-boot/drivers/virtio/
H A Dvirtio_mmio.c23 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_get_config() local
33 ptr[i] = readb(base + offset + i); in virtio_mmio_get_config()
40 b = readb(base + offset); in virtio_mmio_get_config()
44 w = cpu_to_le16(readw(base + offset)); in virtio_mmio_get_config()
48 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
52 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
54 l = cpu_to_le32(readl(base + offset + sizeof(l))); in virtio_mmio_get_config()
68 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_set_config() local
78 writeb(ptr[i], base + offset + i); in virtio_mmio_set_config()
86 writeb(b, base + offset); in virtio_mmio_set_config()
[all …]
/openbmc/phosphor-webui/app/common/styles/base/
H A Dcolors.scss37 $base-01--01: $color--blue-100;
38 $base-01--02: $color--blue-50;
39 $base-01--03: $color--blue-40;
40 $base-01--04: $color--blue-30;
41 $base-01--05: $color--blue-20;
43 $base-02--01: $color--grey-100;
44 $base-02--02: $color--grey-80;
45 $base-02--03: $color--grey-60;
46 $base-02--04: $color--grey-40;
47 $base-02--05: $color--grey-30;
[all …]
/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dbsec.c58 static u32 bsec_check_error(u32 base, u32 otp) in bsec_check_error() argument
66 if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) in bsec_check_error()
68 else if (readl(base + BSEC_ERROR_OFF + bank) & bit) in bsec_check_error()
97 static bool bsec_read_SR_lock(u32 base, u32 otp) in bsec_read_SR_lock() argument
99 return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); in bsec_read_SR_lock()
108 static bool bsec_read_SP_lock(u32 base, u32 otp) in bsec_read_SP_lock() argument
110 return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); in bsec_read_SP_lock()
119 static bool bsec_read_SW_lock(u32 base, u32 otp) in bsec_read_SW_lock() argument
121 return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); in bsec_read_SW_lock()
130 static int bsec_power_safmem(u32 base, bool power) in bsec_power_safmem() argument
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8m-base.inc2 # Defaults for ARMv8-m.base
4 DEFAULTTUNE ?= "armv8m-base"
6 TUNEVALID[armv8m-base] = "Enable instructions for ARMv8-m.base"
7 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8m-base', ' -march=armv8-m.base', …
8 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8m-base', 'armv8m-base:', '', d)}"
10 TUNECONFLICTS[armv8m-base] = "armv4 armv5 armv6 armv7a"
14 AVAILTUNES += "armv8m-base"
15 ARMPKGARCH:tune-armv8m-base = "armv8m-base"
16 TUNE_FEATURES:tune-armv8m-base = "armv8m-base"
17 PACKAGE_EXTRA_ARCHS:tune-armv8m-base = "armv8m-base"
/openbmc/openbmc/poky/meta/recipes-multimedia/gstreamer/
H A Dgstreamer1.0-meta-base.bb12 DEPENDS = "gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-good ${DEPENDS_UGLY} ${DEPEN…
15 gstreamer1.0-meta-base \
16 gstreamer1.0-meta-x11-base \
21 ALLOW_EMPTY:gstreamer1.0-meta-base = "1"
22 ALLOW_EMPTY:gstreamer1.0-meta-x11-base = "1"
27 RDEPENDS:gstreamer1.0-meta-base = "\
28 ${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'gstreamer1.0-meta-x11-base', '', d)} \
30 gstreamer1.0-plugins-base-playback \
31 gstreamer1.0-plugins-base-gio \
32 ${@bb.utils.contains('COMBINED_FEATURES', 'alsa', 'gstreamer1.0-plugins-base-alsa', '',d)} \
[all …]

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