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/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv7m.inc4 DEFAULTTUNE ?= "armv7m"
6 TUNEVALID[armv7m] = "Enable instructions for ARMv7-m"
7 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv7m', ' -march=armv7-m', '', d)}"
8 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv7m', 'armv7m:', '', d)}"
10 TUNECONFLICTS[armv7m] = "armv4 armv5 armv6 armv7a"
14 AVAILTUNES += "armv7m"
15 ARMPKGARCH:tune-armv7m = "armv7m"
16 TUNE_FEATURES:tune-armv7m = "armv7m"
17 PACKAGE_EXTRA_ARCHS:tune-armv7m = "armv7m"
H A Darch-armv7em.inc12 require conf/machine/include/arm/arch-armv7m.inc
H A Darch-armv8m-base.inc12 require conf/machine/include/arm/arch-armv7m.inc
H A Dfeature-arm-thumb.inc32 # what about armv7m devices which don't support -marm (e.g. Cortex-M3)?
/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c51 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f100_soc_initfn()
69 DeviceState *dev, *armv7m; in stm32f100_soc_realize() local
116 armv7m = DEVICE(&s->armv7m); in stm32f100_soc_realize()
117 qdev_prop_set_uint32(armv7m, "num-irq", 61); in stm32f100_soc_realize()
118 qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); in stm32f100_soc_realize()
119 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); in stm32f100_soc_realize()
120 qdev_prop_set_bit(armv7m, "enable-bitband", true); in stm32f100_soc_realize()
121 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f100_soc_realize()
122 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in stm32f100_soc_realize()
123 object_property_set_link(OBJECT(&s->armv7m), "memory", in stm32f100_soc_realize()
[all …]
H A Dmsf2-soc.c66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
85 DeviceState *dev, *armv7m; in m2sxxx_soc_realize() local
135 armv7m = DEVICE(&s->armv7m); in m2sxxx_soc_realize()
136 qdev_prop_set_uint32(armv7m, "num-irq", 81); in m2sxxx_soc_realize()
137 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); in m2sxxx_soc_realize()
138 qdev_prop_set_bit(armv7m, "enable-bitband", true); in m2sxxx_soc_realize()
139 qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); in m2sxxx_soc_realize()
140 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in m2sxxx_soc_realize()
141 object_property_set_link(OBJECT(&s->armv7m), "memory", in m2sxxx_soc_realize()
143 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { in m2sxxx_soc_realize()
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H A Dstm32f205_soc.c55 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f205_soc_initfn()
86 DeviceState *dev, *armv7m; in stm32f205_soc_realize() local
128 armv7m = DEVICE(&s->armv7m); in stm32f205_soc_realize()
129 qdev_prop_set_uint32(armv7m, "num-irq", 96); in stm32f205_soc_realize()
130 qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); in stm32f205_soc_realize()
131 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); in stm32f205_soc_realize()
132 qdev_prop_set_bit(armv7m, "enable-bitband", true); in stm32f205_soc_realize()
133 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f205_soc_realize()
134 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in stm32f205_soc_realize()
135 object_property_set_link(OBJECT(&s->armv7m), "memory", in stm32f205_soc_realize()
[all …]
H A Dstm32f405_soc.c61 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f405_soc_initfn()
95 DeviceState *dev, *armv7m; in stm32f405_soc_realize() local
153 armv7m = DEVICE(&s->armv7m); in stm32f405_soc_realize()
154 qdev_prop_set_uint32(armv7m, "num-irq", 96); in stm32f405_soc_realize()
155 qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); in stm32f405_soc_realize()
156 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); in stm32f405_soc_realize()
157 qdev_prop_set_bit(armv7m, "enable-bitband", true); in stm32f405_soc_realize()
158 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f405_soc_realize()
159 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in stm32f405_soc_realize()
160 object_property_set_link(OBJECT(&s->armv7m), "memory", in stm32f405_soc_realize()
[all …]
H A Dmps2.c73 ARMv7MState armv7m; member
141 DeviceState *armv7m, *sccdev; in mps2_common_init() local
222 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); in mps2_common_init()
223 armv7m = DEVICE(&mms->armv7m); in mps2_common_init()
228 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
231 qdev_prop_set_uint32(armv7m, "num-irq", 64); in mps2_common_init()
236 qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); in mps2_common_init()
237 qdev_connect_clock_in(armv7m, "refclk", mms->refclk); in mps2_common_init()
238 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); in mps2_common_init()
239 qdev_prop_set_bit(armv7m, "enable-bitband", true); in mps2_common_init()
[all …]
H A Dstm32l4x5_soc.c172 DeviceState *armv7m, *dev; in stm32l4x5_soc_realize() local
199 object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32l4x5_soc_realize()
200 armv7m = DEVICE(&s->armv7m); in stm32l4x5_soc_realize()
201 qdev_prop_set_uint32(armv7m, "num-irq", 96); in stm32l4x5_soc_realize()
202 qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); in stm32l4x5_soc_realize()
203 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); in stm32l4x5_soc_realize()
204 qdev_prop_set_bit(armv7m, "enable-bitband", true); in stm32l4x5_soc_realize()
205 qdev_connect_clock_in(armv7m, "cpuclk", in stm32l4x5_soc_realize()
207 qdev_connect_clock_in(armv7m, "refclk", in stm32l4x5_soc_realize()
209 object_property_set_link(OBJECT(&s->armv7m), "memory", in stm32l4x5_soc_realize()
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H A Daspeed_ast10x0.c107 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); in aspeed_soc_ast1030_get_irq()
123 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); in aspeed_soc_ast1030_init()
193 DeviceState *armv7m; in aspeed_soc_ast1030_realize() local
212 armv7m = DEVICE(&a->armv7m); in aspeed_soc_ast1030_realize()
213 qdev_prop_set_uint32(armv7m, "num-irq", 256); in aspeed_soc_ast1030_realize()
214 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); in aspeed_soc_ast1030_realize()
215 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in aspeed_soc_ast1030_realize()
216 object_property_set_link(OBJECT(&a->armv7m), "memory", in aspeed_soc_ast1030_realize()
218 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); in aspeed_soc_ast1030_realize()
222 CPU(a->armv7m.cpu)->cpu_index); in aspeed_soc_ast1030_realize()
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H A Darmsse.c729 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], in armsse_init()
731 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type); in armsse_init()
902 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); in armsse_get_common_irq_in()
988 DeviceState *cpudev = DEVICE(&s->armv7m[i]); in armsse_realize()
989 Object *cpuobj = OBJECT(&s->armv7m[i]); in armsse_realize()
1102 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); in armsse_realize()
1205 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); in armsse_realize()
1404 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); in armsse_realize()
H A Dmeson.build22 arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm3.inc9 require conf/machine/include/arm/arch-armv7m.inc
13 TUNE_FEATURES:tune-cortexm3 = "${TUNE_FEATURES:tune-armv7m} cortexm3"
14 PACKAGE_EXTRA_ARCHS:tune-cortexm3 = "${PACKAGE_EXTRA_ARCHS:tune-armv7m} cortexm3"
/openbmc/u-boot/arch/arm/dts/
H A Darmv7-m.dtsi5 compatible = "arm,armv7m-nvic";
12 compatible = "arm,armv7m-systick";
/openbmc/linux/arch/arm/boot/dts/
H A Darmv7-m.dtsi4 compatible = "arm,armv7m-nvic";
11 compatible = "arm,armv7m-systick";
/openbmc/qemu/include/hw/arm/
H A Dstm32f100_soc.h48 ARMv7MState armv7m; member
H A Dmsf2-soc.h52 ARMv7MState armv7m; member
H A Dstm32f205_soc.h54 ARMv7MState armv7m; member
H A Dstm32l4x5_soc.h51 ARMv7MState armv7m; member
H A Dstm32f405_soc.h57 ARMv7MState armv7m; member
H A Darmsse.h155 ARMv7MState armv7m[SSE_MAX_CPUS]; member
H A Daspeed_soc.h152 ARMv7MState armv7m; member
/openbmc/openbmc/poky/meta/classes-recipe/
H A Drust-common.bbclass34 v7=frozenset(['armv7a', 'armv7r', 'armv7m', 'armv7ve'])
/openbmc/u-boot/arch/arm/
H A DKconfig275 default "armv7m" if CPU_V7M

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