10f76debdSAlexandre Iooss /* 20f76debdSAlexandre Iooss * STM32F100 SoC 30f76debdSAlexandre Iooss * 40f76debdSAlexandre Iooss * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> 50f76debdSAlexandre Iooss * 60f76debdSAlexandre Iooss * Permission is hereby granted, free of charge, to any person obtaining a copy 70f76debdSAlexandre Iooss * of this software and associated documentation files (the "Software"), to deal 80f76debdSAlexandre Iooss * in the Software without restriction, including without limitation the rights 90f76debdSAlexandre Iooss * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 100f76debdSAlexandre Iooss * copies of the Software, and to permit persons to whom the Software is 110f76debdSAlexandre Iooss * furnished to do so, subject to the following conditions: 120f76debdSAlexandre Iooss * 130f76debdSAlexandre Iooss * The above copyright notice and this permission notice shall be included in 140f76debdSAlexandre Iooss * all copies or substantial portions of the Software. 150f76debdSAlexandre Iooss * 160f76debdSAlexandre Iooss * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 170f76debdSAlexandre Iooss * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 180f76debdSAlexandre Iooss * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 190f76debdSAlexandre Iooss * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 200f76debdSAlexandre Iooss * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 210f76debdSAlexandre Iooss * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 220f76debdSAlexandre Iooss * THE SOFTWARE. 230f76debdSAlexandre Iooss */ 240f76debdSAlexandre Iooss 250f76debdSAlexandre Iooss #ifndef HW_ARM_STM32F100_SOC_H 260f76debdSAlexandre Iooss #define HW_ARM_STM32F100_SOC_H 270f76debdSAlexandre Iooss 280f76debdSAlexandre Iooss #include "hw/char/stm32f2xx_usart.h" 290f76debdSAlexandre Iooss #include "hw/ssi/stm32f2xx_spi.h" 300f76debdSAlexandre Iooss #include "hw/arm/armv7m.h" 310f76debdSAlexandre Iooss #include "qom/object.h" 32*b5ff0c61SPeter Maydell #include "hw/clock.h" 330f76debdSAlexandre Iooss 340f76debdSAlexandre Iooss #define TYPE_STM32F100_SOC "stm32f100-soc" 350f76debdSAlexandre Iooss OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) 360f76debdSAlexandre Iooss 370f76debdSAlexandre Iooss #define STM_NUM_USARTS 3 380f76debdSAlexandre Iooss #define STM_NUM_SPIS 2 390f76debdSAlexandre Iooss 400f76debdSAlexandre Iooss #define FLASH_BASE_ADDRESS 0x08000000 410f76debdSAlexandre Iooss #define FLASH_SIZE (128 * 1024) 420f76debdSAlexandre Iooss #define SRAM_BASE_ADDRESS 0x20000000 430f76debdSAlexandre Iooss #define SRAM_SIZE (8 * 1024) 440f76debdSAlexandre Iooss 450f76debdSAlexandre Iooss struct STM32F100State { 460f76debdSAlexandre Iooss SysBusDevice parent_obj; 470f76debdSAlexandre Iooss 480f76debdSAlexandre Iooss ARMv7MState armv7m; 490f76debdSAlexandre Iooss 500f76debdSAlexandre Iooss STM32F2XXUsartState usart[STM_NUM_USARTS]; 510f76debdSAlexandre Iooss STM32F2XXSPIState spi[STM_NUM_SPIS]; 52cabc613fSPeter Maydell 53cabc613fSPeter Maydell MemoryRegion sram; 54cabc613fSPeter Maydell MemoryRegion flash; 55cabc613fSPeter Maydell MemoryRegion flash_alias; 56*b5ff0c61SPeter Maydell 57*b5ff0c61SPeter Maydell Clock *sysclk; 58*b5ff0c61SPeter Maydell Clock *refclk; 590f76debdSAlexandre Iooss }; 600f76debdSAlexandre Iooss 610f76debdSAlexandre Iooss #endif 62