| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun4i.c | 296 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
298 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
338 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); in mctl_setup_dram_clock()
340 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
346 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); in mctl_setup_dram_clock()
348 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
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| H A D | cpu_info.c | 27 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); in sunxi_get_ss_bonding_id()
33 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); in sunxi_get_ss_bonding_id()
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| H A D | clock_sun4i.c | 38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
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| H A D | dram_sun8i_a83t.c | 397 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
411 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| H A D | dram_sun9i.c | 275 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
282 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| H A D | dram_sunxi_dw.c | 373 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
403 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| H A D | clock_sun6i.c | 57 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
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| H A D | dram_sun8i_a33.c | 315 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| H A D | dram_sun8i_a23.c | 71 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| H A D | dram_sun6i.c | 48 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
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| /openbmc/u-boot/board/sunxi/ |
| H A D | gmac.c | 18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
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| H A D | board.c | 355 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_clock_setup()
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | sunxi_nand_spl.c | 541 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_deselect()
545 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); in nand_deselect()
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| H A D | sunxi_nand.c | 307 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); in sunxi_nfc_set_clk_rate()
311 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); in sunxi_nfc_set_clk_rate()
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | clock_sun9i.h | 83 u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ member
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| H A D | clock_sun8i_a83t.h | 38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ member
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| H A D | clock_sun4i.h | 36 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ member
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| H A D | clock_sun6i.h | 38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ member
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| /openbmc/u-boot/drivers/net/ |
| H A D | sunxi_emac.c | 520 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); in sunxi_emac_board_setup()
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| H A D | sun8i_emac.c | 674 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); in sun8i_emac_board_setup()
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | sunxi_mmc.c | 547 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
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