Home
last modified time | relevance | path

Searched refs:_id (Results 1 – 25 of 406) sorted by relevance

12345678910>>...17

/openbmc/linux/include/linux/soc/pxa/
H A Dcpu.h62 _id == 0x2120; \
68 _id <= 0x2105; \
74 _id == 0x2d06; \
80 _id == 0x2100; \
93 _id == 0x411; \
103 _id == 0x688; \
113 _id == 0x689; \
123 _id == 0x603 || _id == 0x682; \
133 _id == 0x683; \
143 _id == 0x693; \
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h126 #define DEF_TYPE(_name, _id, _type...) \ argument
127 { .name = _name, .id = _id, .type = _type }
129 DEF_TYPE(_name, _id, _type, .parent = _parent)
130 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
132 #define DEF_INPUT(_name, _id) \ argument
133 DEF_TYPE(_name, _id, CLK_TYPE_IN)
189 .id = MOD_CLK_BASE + (_id), \
215 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
216 [_id] = { \
221 #define DEF_RST(_id, _off, _bit) \ argument
[all …]
H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
57 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
63 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument
64 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
66 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ argument
[all …]
H A Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \ argument
45 { .name = _name, .id = _id, .type = _type }
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
49 #define DEF_INPUT(_name, _id) \ argument
50 DEF_TYPE(_name, _id, CLK_TYPE_IN)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
57 #define DEF_RATE(_name, _id, _rate) \ argument
[all …]
H A Drcar-gen4-cpg.h36 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
37 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
39 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
40 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
42 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
43 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
47 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
48 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
50 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
51 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
/openbmc/linux/arch/powerpc/include/asm/
H A Dperf_event_server.h170 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix argument
171 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr argument
173 #define EVENT_ATTR(_name, _id, _suffix) \ argument
174 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
177 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) argument
178 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) argument
180 #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) argument
181 #define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c) argument
183 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) argument
184 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) argument
/openbmc/linux/drivers/clk/samsung/
H A Dclk.h43 #define ALIAS(_id, dname, a) \ argument
45 .id = _id, \
70 .id = _id, \
97 .id = _id, \
131 .id = _id, \
143 __MUX(_id, cname, pnames, o, s, w, 0, 0)
172 .id = _id, \
214 .id = _id, \
224 __GATE(_id, cname, pname, o, b, f, gf)
261 .id = _id, \
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mtk.h37 #define GATE_DUMMY(_id, _name) { \ argument
38 .id = _id, \
51 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
52 .id = _id, \
73 .id = _id, \
81 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
114 .id = _id, \
146 MUX_FLAGS(_id, _name, _parents, _reg, \
150 .id = _id, \
164 .id = _id, \
[all …]
H A Dclk-mt8188-infra_ao.c46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
70 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
71 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
77 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
H A Dclk-mt8195-infra_ao.c45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
62 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
63 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
69 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
70 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
76 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
H A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
[all …]
H A Dclk-mt8186-infra_ao.c38 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
39 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
42 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
43 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
45 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
49 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
56 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
63 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
[all …]
H A Dclk-mt8188-vdo1.c46 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
50 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
56 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
59 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
[all …]
H A Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
/openbmc/linux/include/linux/
H A Dmod_devicetable.h441 #define BCMA_CORE(_manuf, _id, _rev, _class) \ argument
442 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
616 #define MDIO_ID_ARGS(_id) \ argument
617 ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
618 ((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, \
619 ((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, \
620 ((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, \
621 ((_id)>>15) & 1, ((_id)>>14) & 1, ((_id)>>13) & 1, ((_id)>>12) & 1, \
622 ((_id)>>11) & 1, ((_id)>>10) & 1, ((_id)>>9) & 1, ((_id)>>8) & 1, \
623 ((_id)>>7) & 1, ((_id)>>6) & 1, ((_id)>>5) & 1, ((_id)>>4) & 1, \
[all …]
/openbmc/linux/drivers/regulator/
H A Dmax77541-regulator.c55 #define MAX77540_BUCK(_id, _ops) \ argument
56 { .id = MAX77541_BUCK ## _id, \
57 .name = "buck"#_id, \
58 .of_match = "buck"#_id, \
61 .enable_mask = MAX77541_BIT_M ## _id ## _EN, \
66 .vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
74 #define MAX77541_BUCK(_id, _ops) \ argument
75 { .id = MAX77541_BUCK ## _id, \
76 .name = "buck"#_id, \
77 .of_match = "buck"#_id, \
[all …]
H A Dmax77826-regulator.c118 #define MAX77826_LDO(_id, _type) \ argument
119 [MAX77826_LDO ## _id] = { \
120 .id = MAX77826_LDO ## _id, \
121 .name = "LDO"#_id, \
122 .of_match = of_match_ptr("LDO"#_id), \
135 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
136 [MAX77826_ ## _id] = { \
137 .id = MAX77826_ ## _id, \
138 .name = #_id, \
139 .of_match = of_match_ptr(#_id), \
[all …]
/openbmc/linux/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
21 .id = _id, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
41 .id = _id, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
61 .id = _id, \
71 .id = _id, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
88 .id = _id, \
121 .id = _id, \
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h65 #define DEF_TYPE(_name, _id, _type...) \ argument
66 { .name = _name, .id = _id, .type = _type }
67 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
68 DEF_TYPE(_name, _id, _type, .parent = _parent)
70 #define DEF_INPUT(_name, _id) \ argument
71 DEF_TYPE(_name, _id, CLK_TYPE_IN)
72 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
73 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
74 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
75 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
[all …]
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-audsys-clk.c29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.h553 .id = _id, \
574 .id = _id, \
596 .id = _id, \
614 .id = _id, \
633 .id = _id, \
651 .id = _id, \
670 .id = _id, \
689 .id = _id, \
706 .id = _id, \
724 .id = _id, \
[all …]
/openbmc/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-audsys-clk.c29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
[all …]
/openbmc/linux/include/rdma/
H A Duverbs_std_types.h19 #define _uobj_check_id(_id) ((_id) * typecheck(u32, _id)) argument
24 #define uobj_get_read(_type, _id, _attrs) \ argument
26 _uobj_check_id(_id), UVERBS_LOOKUP_READ, \
40 #define uobj_get_obj_read(_object, _type, _id, _attrs) \ argument
42 uobj_get_read(_type, _id, _attrs)))
44 #define uobj_get_write(_type, _id, _attrs) \ argument
46 _uobj_check_id(_id), UVERBS_LOOKUP_WRITE, \
51 #define uobj_perform_destroy(_type, _id, _attrs) \ argument
53 _uobj_check_id(_id), _attrs)
58 #define uobj_get_destroy(_type, _id, _attrs) \ argument
[all …]
/openbmc/linux/include/linux/mfd/
H A Dcore.h17 #define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \ argument
28 .id = (_id), \
31 #define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \ argument
32 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
34 #define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \ argument
35 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
37 #define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \ argument
38 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
40 #define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \ argument
41 MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, NULL)

12345678910>>...17