1fce4c7a2SGarmin.Chang // SPDX-License-Identifier: GPL-2.0-only 2fce4c7a2SGarmin.Chang /* 3fce4c7a2SGarmin.Chang * Copyright (c) 2022 MediaTek Inc. 4fce4c7a2SGarmin.Chang * Author: Garmin Chang <garmin.chang@mediatek.com> 5fce4c7a2SGarmin.Chang */ 6fce4c7a2SGarmin.Chang 7fce4c7a2SGarmin.Chang #include <dt-bindings/clock/mediatek,mt8188-clk.h> 8*18eb864fSRunyang Chen #include <dt-bindings/reset/mt8188-resets.h> 9fce4c7a2SGarmin.Chang #include <linux/clk-provider.h> 10fce4c7a2SGarmin.Chang #include <linux/platform_device.h> 11fce4c7a2SGarmin.Chang 12fce4c7a2SGarmin.Chang #include "clk-gate.h" 13fce4c7a2SGarmin.Chang #include "clk-mtk.h" 14fce4c7a2SGarmin.Chang 15fce4c7a2SGarmin.Chang static const struct mtk_gate_regs infra_ao0_cg_regs = { 16fce4c7a2SGarmin.Chang .set_ofs = 0x80, 17fce4c7a2SGarmin.Chang .clr_ofs = 0x84, 18fce4c7a2SGarmin.Chang .sta_ofs = 0x90, 19fce4c7a2SGarmin.Chang }; 20fce4c7a2SGarmin.Chang 21fce4c7a2SGarmin.Chang static const struct mtk_gate_regs infra_ao1_cg_regs = { 22fce4c7a2SGarmin.Chang .set_ofs = 0x88, 23fce4c7a2SGarmin.Chang .clr_ofs = 0x8c, 24fce4c7a2SGarmin.Chang .sta_ofs = 0x94, 25fce4c7a2SGarmin.Chang }; 26fce4c7a2SGarmin.Chang 27fce4c7a2SGarmin.Chang static const struct mtk_gate_regs infra_ao2_cg_regs = { 28fce4c7a2SGarmin.Chang .set_ofs = 0xa4, 29fce4c7a2SGarmin.Chang .clr_ofs = 0xa8, 30fce4c7a2SGarmin.Chang .sta_ofs = 0xac, 31fce4c7a2SGarmin.Chang }; 32fce4c7a2SGarmin.Chang 33fce4c7a2SGarmin.Chang static const struct mtk_gate_regs infra_ao3_cg_regs = { 34fce4c7a2SGarmin.Chang .set_ofs = 0xc0, 35fce4c7a2SGarmin.Chang .clr_ofs = 0xc4, 36fce4c7a2SGarmin.Chang .sta_ofs = 0xc8, 37fce4c7a2SGarmin.Chang }; 38fce4c7a2SGarmin.Chang 39fce4c7a2SGarmin.Chang static const struct mtk_gate_regs infra_ao4_cg_regs = { 40fce4c7a2SGarmin.Chang .set_ofs = 0xe0, 41fce4c7a2SGarmin.Chang .clr_ofs = 0xe4, 42fce4c7a2SGarmin.Chang .sta_ofs = 0xe8, 43fce4c7a2SGarmin.Chang }; 44fce4c7a2SGarmin.Chang 45fce4c7a2SGarmin.Chang #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ 46fce4c7a2SGarmin.Chang GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \ 47fce4c7a2SGarmin.Chang &mtk_clk_gate_ops_setclr, _flag) 48fce4c7a2SGarmin.Chang 49fce4c7a2SGarmin.Chang #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ 50fce4c7a2SGarmin.Chang GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0) 51fce4c7a2SGarmin.Chang 52fce4c7a2SGarmin.Chang #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ 53fce4c7a2SGarmin.Chang GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \ 54fce4c7a2SGarmin.Chang &mtk_clk_gate_ops_setclr, _flag) 55fce4c7a2SGarmin.Chang 56fce4c7a2SGarmin.Chang #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ 57fce4c7a2SGarmin.Chang GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) 58fce4c7a2SGarmin.Chang 59fce4c7a2SGarmin.Chang #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ 60fce4c7a2SGarmin.Chang GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 61fce4c7a2SGarmin.Chang 62fce4c7a2SGarmin.Chang #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ 63fce4c7a2SGarmin.Chang GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ 64fce4c7a2SGarmin.Chang &mtk_clk_gate_ops_setclr, _flag) 65fce4c7a2SGarmin.Chang 66fce4c7a2SGarmin.Chang #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ 67fce4c7a2SGarmin.Chang GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ 68fce4c7a2SGarmin.Chang &mtk_clk_gate_ops_setclr, _flag) 69fce4c7a2SGarmin.Chang 70fce4c7a2SGarmin.Chang #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ 71fce4c7a2SGarmin.Chang GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0) 72fce4c7a2SGarmin.Chang 73fce4c7a2SGarmin.Chang #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ 74fce4c7a2SGarmin.Chang GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \ 75fce4c7a2SGarmin.Chang &mtk_clk_gate_ops_setclr, _flag) 76fce4c7a2SGarmin.Chang 77fce4c7a2SGarmin.Chang #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ 78fce4c7a2SGarmin.Chang GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0) 79fce4c7a2SGarmin.Chang 80fce4c7a2SGarmin.Chang static const struct mtk_gate infra_ao_clks[] = { 81fce4c7a2SGarmin.Chang /* INFRA_AO0 */ 82fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0), 83fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1), 84fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2), 85fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3), 86fce4c7a2SGarmin.Chang /* infra_ao_sej is main clock is for secure engine with JTAG support */ 87fce4c7a2SGarmin.Chang GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL), 88fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6), 89fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8), 90fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9), 91fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10), 92fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15), 93fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16), 94fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17), 95fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18), 96fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19), 97fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21), 98fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22), 99fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23), 100fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24), 101fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25), 102fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26), 103fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27), 104fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28), 105fce4c7a2SGarmin.Chang GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29), 106fce4c7a2SGarmin.Chang /* INFRA_AO1 */ 107fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0), 108fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1), 109fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2), 110fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4), 111fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5), 112fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6), 113fce4c7a2SGarmin.Chang /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ 114fce4c7a2SGarmin.Chang GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc", 115fce4c7a2SGarmin.Chang "clk26m", 7, CLK_IS_CRITICAL), 116fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9), 117fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10), 118fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11), 119fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12), 120fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13), 121fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15), 122fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16), 123fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17), 124fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18), 125fce4c7a2SGarmin.Chang /* infra_ao_dapc is for device access permission control module */ 126fce4c7a2SGarmin.Chang GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc", 127fce4c7a2SGarmin.Chang "top_axi", 20, CLK_IS_CRITICAL), 128fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23), 129fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24), 130fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25), 131fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26), 132fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29), 133fce4c7a2SGarmin.Chang GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31), 134fce4c7a2SGarmin.Chang /* INFRA_AO2 */ 135fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0), 136fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2), 137fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3), 138fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4), 139fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6), 140fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9), 141fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10), 142fce4c7a2SGarmin.Chang GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm", 143fce4c7a2SGarmin.Chang "top_sspm", 15, CLK_IS_CRITICAL), 144fce4c7a2SGarmin.Chang GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk", 145fce4c7a2SGarmin.Chang "top_axi", 17, CLK_IS_CRITICAL), 146fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18), 147fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), 148fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26), 149fce4c7a2SGarmin.Chang GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27), 150fce4c7a2SGarmin.Chang /* INFRA_AO3 */ 151fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0), 152fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1), 153fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2), 154fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5), 155fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7), 156fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8), 157fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9), 158fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10), 159fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15), 160fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16), 161fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17), 162fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20), 163fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24), 164fce4c7a2SGarmin.Chang /* infra_ao_dapc_sync is for device access permission control module */ 165fce4c7a2SGarmin.Chang GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync", 166fce4c7a2SGarmin.Chang "top_axi", 25, CLK_IS_CRITICAL), 167fce4c7a2SGarmin.Chang GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26), 168fce4c7a2SGarmin.Chang /* INFRA_AO4 */ 169fce4c7a2SGarmin.Chang /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ 170fce4c7a2SGarmin.Chang GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set", 171fce4c7a2SGarmin.Chang "top_axi", 0, CLK_IS_CRITICAL), 172fce4c7a2SGarmin.Chang GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set", 173fce4c7a2SGarmin.Chang "top_axi", 1, CLK_IS_CRITICAL), 174fce4c7a2SGarmin.Chang GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", 175fce4c7a2SGarmin.Chang "pextp_pipe", 7), 176fce4c7a2SGarmin.Chang GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, 177fce4c7a2SGarmin.Chang "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), 178fce4c7a2SGarmin.Chang }; 179fce4c7a2SGarmin.Chang 180*18eb864fSRunyang Chen static u16 infra_ao_rst_ofs[] = { 181*18eb864fSRunyang Chen INFRA_RST0_SET_OFFSET, 182*18eb864fSRunyang Chen INFRA_RST1_SET_OFFSET, 183*18eb864fSRunyang Chen INFRA_RST2_SET_OFFSET, 184*18eb864fSRunyang Chen INFRA_RST3_SET_OFFSET, 185*18eb864fSRunyang Chen INFRA_RST4_SET_OFFSET, 186*18eb864fSRunyang Chen }; 187*18eb864fSRunyang Chen 188*18eb864fSRunyang Chen static u16 infra_ao_idx_map[] = { 189*18eb864fSRunyang Chen [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, 190*18eb864fSRunyang Chen [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, 191*18eb864fSRunyang Chen [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5, 192*18eb864fSRunyang Chen }; 193*18eb864fSRunyang Chen 194*18eb864fSRunyang Chen static const struct mtk_clk_rst_desc infra_ao_rst_desc = { 195*18eb864fSRunyang Chen .version = MTK_RST_SET_CLR, 196*18eb864fSRunyang Chen .rst_bank_ofs = infra_ao_rst_ofs, 197*18eb864fSRunyang Chen .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 198*18eb864fSRunyang Chen .rst_idx_map = infra_ao_idx_map, 199*18eb864fSRunyang Chen .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 200*18eb864fSRunyang Chen }; 201*18eb864fSRunyang Chen 202fce4c7a2SGarmin.Chang static const struct mtk_clk_desc infra_ao_desc = { 203fce4c7a2SGarmin.Chang .clks = infra_ao_clks, 204fce4c7a2SGarmin.Chang .num_clks = ARRAY_SIZE(infra_ao_clks), 205*18eb864fSRunyang Chen .rst_desc = &infra_ao_rst_desc, 206fce4c7a2SGarmin.Chang }; 207fce4c7a2SGarmin.Chang 208fce4c7a2SGarmin.Chang static const struct of_device_id of_match_clk_mt8188_infra_ao[] = { 209fce4c7a2SGarmin.Chang { .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc }, 210fce4c7a2SGarmin.Chang { /* sentinel */ } 211fce4c7a2SGarmin.Chang }; 212fce4c7a2SGarmin.Chang MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao); 213fce4c7a2SGarmin.Chang 214fce4c7a2SGarmin.Chang static struct platform_driver clk_mt8188_infra_ao_drv = { 215fce4c7a2SGarmin.Chang .probe = mtk_clk_simple_probe, 216fce4c7a2SGarmin.Chang .remove_new = mtk_clk_simple_remove, 217fce4c7a2SGarmin.Chang .driver = { 218fce4c7a2SGarmin.Chang .name = "clk-mt8188-infra_ao", 219fce4c7a2SGarmin.Chang .of_match_table = of_match_clk_mt8188_infra_ao, 220fce4c7a2SGarmin.Chang }, 221fce4c7a2SGarmin.Chang }; 222fce4c7a2SGarmin.Chang module_platform_driver(clk_mt8188_infra_ao_drv); 223fce4c7a2SGarmin.Chang MODULE_LICENSE("GPL"); 224