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Searched refs:WREG32_FIELD15_PREREG (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c185 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_3_init_system_aperture_regs()
393 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
H A Dnbio_v7_9.c241 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v7_9_enable_doorbell_aperture()
393 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, in nbio_v7_9_enable_doorbell_interrupt()
H A Dgfxhub_v3_0.c180 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_init_system_aperture_regs()
400 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
H A Dgfx_v9_4_3.c204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, in gfx_v9_4_3_init_golden_registers()
207 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, in gfx_v9_4_3_init_golden_registers()
1029 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_4_3_xcc_enable_save_restore_machine()
1176 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1193 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1196 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1212 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
1606 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_kiq_init_register()
1987 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_fini()
2769 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_reg_fault_state()
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H A Dsoc15_common.h58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ macro
H A Dnbio_v4_3.c155 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v4_3_enable_doorbell_aperture()
H A Dgfx_v11_0.c1708 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
1788 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
1790 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
1823 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
3879 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
3973 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
5905 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
5924 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_inst_fault_state()
H A Damdgpu_amdkfd_gfx_v11.c501 WREG32_FIELD15_PREREG(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v11()