139def24fSHawking Zhang /*
239def24fSHawking Zhang * Copyright 2022 Advanced Micro Devices, Inc.
339def24fSHawking Zhang *
439def24fSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a
539def24fSHawking Zhang * copy of this software and associated documentation files (the "Software"),
639def24fSHawking Zhang * to deal in the Software without restriction, including without limitation
739def24fSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
839def24fSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the
939def24fSHawking Zhang * Software is furnished to do so, subject to the following conditions:
1039def24fSHawking Zhang *
1139def24fSHawking Zhang * The above copyright notice and this permission notice shall be included in
1239def24fSHawking Zhang * all copies or substantial portions of the Software.
1339def24fSHawking Zhang *
1439def24fSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1539def24fSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1639def24fSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1739def24fSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1839def24fSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1939def24fSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2039def24fSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE.
2139def24fSHawking Zhang *
2239def24fSHawking Zhang */
2339def24fSHawking Zhang #include "amdgpu.h"
2439def24fSHawking Zhang #include "amdgpu_atombios.h"
2539def24fSHawking Zhang #include "nbio_v7_9.h"
2639def24fSHawking Zhang #include "amdgpu_ras.h"
2739def24fSHawking Zhang
2839def24fSHawking Zhang #include "nbio/nbio_7_9_0_offset.h"
2939def24fSHawking Zhang #include "nbio/nbio_7_9_0_sh_mask.h"
3039def24fSHawking Zhang #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
3139def24fSHawking Zhang #include <uapi/linux/kfd_ioctl.h>
3239def24fSHawking Zhang
33ea2d2f8eSRajneesh Bhardwaj #define NPS_MODE_MASK 0x000000FFL
34ea2d2f8eSRajneesh Bhardwaj
3550709d18SLijo Lazar /* Core 0 Port 0 counter */
3650709d18SLijo Lazar #define smnPCIEP_NAK_COUNTER 0x1A340218
3750709d18SLijo Lazar
3859070fd9SAsad Kamal #define smnPCIE_PERF_CNTL_TXCLK3 0x1A38021c
3959070fd9SAsad Kamal #define smnPCIE_PERF_CNTL_TXCLK7 0x1A380888
4059070fd9SAsad Kamal #define smnPCIE_PERF_COUNT_CNTL 0x1A380200
4159070fd9SAsad Kamal #define smnPCIE_PERF_COUNT0_TXCLK3 0x1A380220
4259070fd9SAsad Kamal #define smnPCIE_PERF_COUNT0_TXCLK7 0x1A38088C
4359070fd9SAsad Kamal #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK3 0x1A3808F8
4459070fd9SAsad Kamal #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK7 0x1A380918
4559070fd9SAsad Kamal
4659070fd9SAsad Kamal
nbio_v7_9_remap_hdp_registers(struct amdgpu_device * adev)4739def24fSHawking Zhang static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
4839def24fSHawking Zhang {
4939def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
5039def24fSHawking Zhang adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
5139def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
5239def24fSHawking Zhang adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
5339def24fSHawking Zhang }
5439def24fSHawking Zhang
nbio_v7_9_get_rev_id(struct amdgpu_device * adev)5539def24fSHawking Zhang static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
5639def24fSHawking Zhang {
5739def24fSHawking Zhang u32 tmp;
5839def24fSHawking Zhang
5939def24fSHawking Zhang tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
6039def24fSHawking Zhang tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0);
6139def24fSHawking Zhang
6239def24fSHawking Zhang return tmp;
6339def24fSHawking Zhang }
6439def24fSHawking Zhang
nbio_v7_9_mc_access_enable(struct amdgpu_device * adev,bool enable)6539def24fSHawking Zhang static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
6639def24fSHawking Zhang {
6739def24fSHawking Zhang if (enable)
6839def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
6939def24fSHawking Zhang BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
7039def24fSHawking Zhang else
7139def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
7239def24fSHawking Zhang }
7339def24fSHawking Zhang
nbio_v7_9_get_memsize(struct amdgpu_device * adev)7439def24fSHawking Zhang static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
7539def24fSHawking Zhang {
7639def24fSHawking Zhang return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
7739def24fSHawking Zhang }
7839def24fSHawking Zhang
nbio_v7_9_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)7939def24fSHawking Zhang static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
8039def24fSHawking Zhang bool use_doorbell, int doorbell_index, int doorbell_size)
8139def24fSHawking Zhang {
8239def24fSHawking Zhang u32 doorbell_range = 0, doorbell_ctrl = 0;
83f8b34a05SLijo Lazar int aid_id, dev_inst;
84f8b34a05SLijo Lazar
85f8b34a05SLijo Lazar dev_inst = GET_INST(SDMA0, instance);
86f8b34a05SLijo Lazar aid_id = adev->sdma.instance[instance].aid_id;
876b22ef25SLe Ma
886b22ef25SLe Ma if (use_doorbell == false)
896b22ef25SLe Ma return;
9039def24fSHawking Zhang
9139def24fSHawking Zhang doorbell_range =
9239def24fSHawking Zhang REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
9339def24fSHawking Zhang BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
9439def24fSHawking Zhang doorbell_range =
9539def24fSHawking Zhang REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
9639def24fSHawking Zhang BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
9739def24fSHawking Zhang doorbell_ctrl =
9839def24fSHawking Zhang REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
9939def24fSHawking Zhang S2A_DOORBELL_PORT1_ENABLE, 1);
10039def24fSHawking Zhang doorbell_ctrl =
10139def24fSHawking Zhang REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
10239def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
10339def24fSHawking Zhang
104f8b34a05SLijo Lazar switch (dev_inst % adev->sdma.num_inst_per_aid) {
10539def24fSHawking Zhang case 0:
1063955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
1076b22ef25SLe Ma 4 * aid_id, doorbell_range);
10839def24fSHawking Zhang
10939def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
11039def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
11139def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0xe);
11239def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
11339def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
11439def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
11539def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
11639def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
11739def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
11839def24fSHawking Zhang 0x1);
119369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
120369576c2SLe Ma aid_id, doorbell_ctrl);
12139def24fSHawking Zhang break;
12239def24fSHawking Zhang case 1:
1233955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
1246b22ef25SLe Ma 4 * aid_id, doorbell_range);
12539def24fSHawking Zhang
12639def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
12739def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
12839def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0x8);
12939def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
13039def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
13139def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
13239def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
13339def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
13439def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
13539def24fSHawking Zhang 0x2);
136369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
137369576c2SLe Ma aid_id, doorbell_ctrl);
13839def24fSHawking Zhang break;
13939def24fSHawking Zhang case 2:
1403955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
1416b22ef25SLe Ma 4 * aid_id, doorbell_range);
14239def24fSHawking Zhang
14339def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
14439def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
14539def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0x9);
14639def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
14739def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
14839def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
14939def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
15039def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
15139def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
15239def24fSHawking Zhang 0x8);
153369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
154369576c2SLe Ma aid_id, doorbell_ctrl);
15539def24fSHawking Zhang break;
15639def24fSHawking Zhang case 3:
1573955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
1586b22ef25SLe Ma 4 * aid_id, doorbell_range);
15939def24fSHawking Zhang
16039def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
16139def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
16239def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0xa);
16339def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
16439def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
16539def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
16639def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
16739def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
16839def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
16939def24fSHawking Zhang 0x9);
170369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
171369576c2SLe Ma aid_id, doorbell_ctrl);
17239def24fSHawking Zhang break;
17339def24fSHawking Zhang default:
17439def24fSHawking Zhang break;
1751ffbc89cSJiapeng Chong }
17639def24fSHawking Zhang
17739def24fSHawking Zhang return;
17839def24fSHawking Zhang }
17939def24fSHawking Zhang
nbio_v7_9_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)18039def24fSHawking Zhang static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
18139def24fSHawking Zhang int doorbell_index, int instance)
18239def24fSHawking Zhang {
18339def24fSHawking Zhang u32 doorbell_range = 0, doorbell_ctrl = 0;
1842e10ced4SJames Zhu u32 aid_id = instance;
18539def24fSHawking Zhang
18639def24fSHawking Zhang if (use_doorbell) {
18739def24fSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range,
18839def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
18939def24fSHawking Zhang BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
19039def24fSHawking Zhang doorbell_index);
19139def24fSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range,
19239def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
19339def24fSHawking Zhang BIF_DOORBELL0_RANGE_SIZE_ENTRY,
19453054e9aSJames Zhu 0x9);
1952e10ced4SJames Zhu if (aid_id)
1962e10ced4SJames Zhu doorbell_range = REG_SET_FIELD(doorbell_range,
1972e10ced4SJames Zhu DOORBELL0_CTRL_ENTRY_0,
1982e10ced4SJames Zhu DOORBELL0_FENCE_ENABLE_ENTRY,
1992e10ced4SJames Zhu 0x4);
20039def24fSHawking Zhang
20139def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
20239def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
20339def24fSHawking Zhang S2A_DOORBELL_PORT1_ENABLE, 1);
20439def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
20539def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
20639def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0x4);
20739def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
20839def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
20939def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
21039def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
21139def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
21253054e9aSJames Zhu S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);
21339def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
21439def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
21539def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
2162e10ced4SJames Zhu
2173955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
2182e10ced4SJames Zhu aid_id, doorbell_range);
219369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
220369576c2SLe Ma aid_id, doorbell_ctrl);
22139def24fSHawking Zhang } else {
22239def24fSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range,
22339def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
22439def24fSHawking Zhang BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
22539def24fSHawking Zhang doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
22639def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
22739def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
22839def24fSHawking Zhang
2293955b141SLe Ma WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
2303955b141SLe Ma aid_id, doorbell_range);
231369576c2SLe Ma WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
232369576c2SLe Ma aid_id, doorbell_ctrl);
2332e10ced4SJames Zhu }
23439def24fSHawking Zhang }
23539def24fSHawking Zhang
nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)23639def24fSHawking Zhang static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
23739def24fSHawking Zhang bool enable)
23839def24fSHawking Zhang {
23939def24fSHawking Zhang /* Enable to allow doorbell pass thru on pre-silicon bare-metal */
24039def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
24139def24fSHawking Zhang WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
24239def24fSHawking Zhang BIF_DOORBELL_APER_EN, enable ? 1 : 0);
24339def24fSHawking Zhang }
24439def24fSHawking Zhang
nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)24539def24fSHawking Zhang static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
24639def24fSHawking Zhang bool enable)
24739def24fSHawking Zhang {
24839def24fSHawking Zhang u32 tmp = 0;
24939def24fSHawking Zhang
25039def24fSHawking Zhang if (enable) {
25139def24fSHawking Zhang tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
25239def24fSHawking Zhang DOORBELL_SELFRING_GPA_APER_EN, 1) |
25339def24fSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
25439def24fSHawking Zhang DOORBELL_SELFRING_GPA_APER_MODE, 1) |
25539def24fSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
25639def24fSHawking Zhang DOORBELL_SELFRING_GPA_APER_SIZE, 0);
25739def24fSHawking Zhang
25839def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
25939def24fSHawking Zhang lower_32_bits(adev->doorbell.base));
26039def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
26139def24fSHawking Zhang upper_32_bits(adev->doorbell.base));
26239def24fSHawking Zhang }
26339def24fSHawking Zhang
26439def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
26539def24fSHawking Zhang }
26639def24fSHawking Zhang
nbio_v7_9_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)26739def24fSHawking Zhang static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
26839def24fSHawking Zhang bool use_doorbell, int doorbell_index)
26939def24fSHawking Zhang {
27039def24fSHawking Zhang u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
27139def24fSHawking Zhang
27239def24fSHawking Zhang if (use_doorbell) {
27339def24fSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
27439def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
27539def24fSHawking Zhang BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
27639def24fSHawking Zhang doorbell_index);
27739def24fSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
27839def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
27939def24fSHawking Zhang BIF_DOORBELL0_RANGE_SIZE_ENTRY,
28040b832aaSMukul Joshi 0x8);
28139def24fSHawking Zhang
28239def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
28339def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
28439def24fSHawking Zhang S2A_DOORBELL_PORT1_ENABLE, 1);
28539def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
28639def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
28739def24fSHawking Zhang S2A_DOORBELL_PORT1_AWID, 0);
28839def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
28939def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
29039def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
29139def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
29239def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
29340b832aaSMukul Joshi S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
29439def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
29539def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
29639def24fSHawking Zhang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
29739def24fSHawking Zhang } else {
29839def24fSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
29939def24fSHawking Zhang DOORBELL0_CTRL_ENTRY_0,
30039def24fSHawking Zhang BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
30139def24fSHawking Zhang ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
30239def24fSHawking Zhang S2A_DOORBELL_ENTRY_1_CTRL,
30339def24fSHawking Zhang S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
30439def24fSHawking Zhang }
30539def24fSHawking Zhang
30639def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
30739def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
30839def24fSHawking Zhang }
30939def24fSHawking Zhang
31039def24fSHawking Zhang
nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)31139def24fSHawking Zhang static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
31239def24fSHawking Zhang bool enable)
31339def24fSHawking Zhang {
31439def24fSHawking Zhang }
31539def24fSHawking Zhang
nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)31639def24fSHawking Zhang static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
31739def24fSHawking Zhang bool enable)
31839def24fSHawking Zhang {
31939def24fSHawking Zhang }
32039def24fSHawking Zhang
nbio_v7_9_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)32139def24fSHawking Zhang static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
32239def24fSHawking Zhang u64 *flags)
32339def24fSHawking Zhang {
32439def24fSHawking Zhang }
32539def24fSHawking Zhang
nbio_v7_9_ih_control(struct amdgpu_device * adev)32639def24fSHawking Zhang static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
32739def24fSHawking Zhang {
32839def24fSHawking Zhang u32 interrupt_cntl;
32939def24fSHawking Zhang
33039def24fSHawking Zhang /* setup interrupt control */
33139def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
33239def24fSHawking Zhang interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
33339def24fSHawking Zhang /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
33439def24fSHawking Zhang * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
33539def24fSHawking Zhang */
33639def24fSHawking Zhang interrupt_cntl =
33739def24fSHawking Zhang REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
33839def24fSHawking Zhang /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
33939def24fSHawking Zhang interrupt_cntl =
34039def24fSHawking Zhang REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
34139def24fSHawking Zhang WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
34239def24fSHawking Zhang }
34339def24fSHawking Zhang
nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device * adev)34439def24fSHawking Zhang static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
34539def24fSHawking Zhang {
34639def24fSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
34739def24fSHawking Zhang }
34839def24fSHawking Zhang
nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device * adev)34939def24fSHawking Zhang static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
35039def24fSHawking Zhang {
35139def24fSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
35239def24fSHawking Zhang }
35339def24fSHawking Zhang
nbio_v7_9_get_pcie_index_offset(struct amdgpu_device * adev)35439def24fSHawking Zhang static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
35539def24fSHawking Zhang {
35639def24fSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
35739def24fSHawking Zhang }
35839def24fSHawking Zhang
nbio_v7_9_get_pcie_data_offset(struct amdgpu_device * adev)35939def24fSHawking Zhang static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
36039def24fSHawking Zhang {
36139def24fSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
36239def24fSHawking Zhang }
36339def24fSHawking Zhang
nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device * adev)3640c552ed3SLe Ma static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
3650c552ed3SLe Ma {
3660c552ed3SLe Ma return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
3670c552ed3SLe Ma }
3680c552ed3SLe Ma
36939def24fSHawking Zhang const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
37039def24fSHawking Zhang .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
37139def24fSHawking Zhang .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
37239def24fSHawking Zhang .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
37339def24fSHawking Zhang .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
37439def24fSHawking Zhang .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
37539def24fSHawking Zhang .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
37639def24fSHawking Zhang .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
37739def24fSHawking Zhang .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
37839def24fSHawking Zhang .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
37939def24fSHawking Zhang .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
38039def24fSHawking Zhang .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
38139def24fSHawking Zhang .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
38239def24fSHawking Zhang .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
38339def24fSHawking Zhang .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
38439def24fSHawking Zhang .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
38539def24fSHawking Zhang .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
38639def24fSHawking Zhang .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
38739def24fSHawking Zhang .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
38839def24fSHawking Zhang };
38939def24fSHawking Zhang
nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device * adev,bool enable)39039def24fSHawking Zhang static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
39139def24fSHawking Zhang bool enable)
39239def24fSHawking Zhang {
39339def24fSHawking Zhang WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
39439def24fSHawking Zhang DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
39539def24fSHawking Zhang }
39639def24fSHawking Zhang
nbio_v7_9_get_compute_partition_mode(struct amdgpu_device * adev)3976c882a57SNathan Chancellor static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
39898a54e88SLe Ma {
399cd321e6fSLijo Lazar u32 tmp, px;
40098a54e88SLe Ma
401cd321e6fSLijo Lazar tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
402cd321e6fSLijo Lazar px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
403cd321e6fSLijo Lazar PARTITION_MODE);
40498a54e88SLe Ma
405fe381726SLijo Lazar return px;
40698a54e88SLe Ma }
40798a54e88SLe Ma
nbio_v7_9_get_memory_partition_mode(struct amdgpu_device * adev,u32 * supp_modes)4086c882a57SNathan Chancellor static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
4096c882a57SNathan Chancellor u32 *supp_modes)
410ea2d2f8eSRajneesh Bhardwaj {
411ea2d2f8eSRajneesh Bhardwaj u32 tmp;
4120f2e1d62SLijo Lazar
413ea2d2f8eSRajneesh Bhardwaj tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
414ea2d2f8eSRajneesh Bhardwaj tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
415ea2d2f8eSRajneesh Bhardwaj
4160f2e1d62SLijo Lazar if (supp_modes) {
4170f2e1d62SLijo Lazar *supp_modes =
4180f2e1d62SLijo Lazar RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
4190f2e1d62SLijo Lazar }
4200f2e1d62SLijo Lazar
421ea2d2f8eSRajneesh Bhardwaj return ffs(tmp);
422ea2d2f8eSRajneesh Bhardwaj }
423ea2d2f8eSRajneesh Bhardwaj
nbio_v7_9_init_registers(struct amdgpu_device * adev)42489fb3020SShiwu Zhang static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
42589fb3020SShiwu Zhang {
42689fb3020SShiwu Zhang u32 inst_mask;
42789fb3020SShiwu Zhang int i;
42889fb3020SShiwu Zhang
429*c19453ccSLijo Lazar if (amdgpu_sriov_vf(adev))
430*c19453ccSLijo Lazar adev->rmmio_remap.reg_offset =
431*c19453ccSLijo Lazar SOC15_REG_OFFSET(
432*c19453ccSLijo Lazar NBIO, 0,
433*c19453ccSLijo Lazar regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
434*c19453ccSLijo Lazar << 2;
43589fb3020SShiwu Zhang WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
43689fb3020SShiwu Zhang 0xff & ~(adev->gfx.xcc_mask));
43789fb3020SShiwu Zhang
438a3ffabb2SLijo Lazar WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
439a3ffabb2SLijo Lazar
44089fb3020SShiwu Zhang inst_mask = adev->aid_mask & ~1U;
44189fb3020SShiwu Zhang for_each_inst(i, inst_mask) {
44289fb3020SShiwu Zhang WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
44389fb3020SShiwu Zhang XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
44489fb3020SShiwu Zhang
44589fb3020SShiwu Zhang }
4468f177893SLijo Lazar
4478f177893SLijo Lazar if (!amdgpu_sriov_vf(adev)) {
4488f177893SLijo Lazar u32 baco_cntl;
4498f177893SLijo Lazar for_each_inst(i, adev->aid_mask) {
4508f177893SLijo Lazar baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
4518f177893SLijo Lazar if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
4528f177893SLijo Lazar BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
4538f177893SLijo Lazar baco_cntl &= ~(
4548f177893SLijo Lazar BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
4558f177893SLijo Lazar BIF_BX0_BACO_CNTL__BACO_EN_MASK);
4568f177893SLijo Lazar dev_dbg(adev->dev,
4578f177893SLijo Lazar "Unsetting baco dummy mode %x",
4588f177893SLijo Lazar baco_cntl);
4598f177893SLijo Lazar WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
4608f177893SLijo Lazar baco_cntl);
4618f177893SLijo Lazar }
4628f177893SLijo Lazar }
4638f177893SLijo Lazar }
46489fb3020SShiwu Zhang }
46589fb3020SShiwu Zhang
nbio_v7_9_get_pcie_replay_count(struct amdgpu_device * adev)46650709d18SLijo Lazar static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)
46750709d18SLijo Lazar {
46850709d18SLijo Lazar u32 val, nak_r, nak_g;
46950709d18SLijo Lazar
47050709d18SLijo Lazar if (adev->flags & AMD_IS_APU)
47150709d18SLijo Lazar return 0;
47250709d18SLijo Lazar
47350709d18SLijo Lazar /* Get the number of NAKs received and generated */
47450709d18SLijo Lazar val = RREG32_PCIE(smnPCIEP_NAK_COUNTER);
47550709d18SLijo Lazar nak_r = val & 0xFFFF;
47650709d18SLijo Lazar nak_g = val >> 16;
47750709d18SLijo Lazar
47850709d18SLijo Lazar /* Add the total number of NAKs, i.e the number of replays */
47950709d18SLijo Lazar return (nak_r + nak_g);
48050709d18SLijo Lazar }
48150709d18SLijo Lazar
nbio_v7_9_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)48259070fd9SAsad Kamal static void nbio_v7_9_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
48359070fd9SAsad Kamal uint64_t *count1)
48459070fd9SAsad Kamal {
48559070fd9SAsad Kamal uint32_t perfctrrx = 0;
48659070fd9SAsad Kamal uint32_t perfctrtx = 0;
48759070fd9SAsad Kamal
48859070fd9SAsad Kamal /* This reports 0 on APUs, so return to avoid writing/reading registers
48959070fd9SAsad Kamal * that may or may not be different from their GPU counterparts
49059070fd9SAsad Kamal */
49159070fd9SAsad Kamal if (adev->flags & AMD_IS_APU)
49259070fd9SAsad Kamal return;
49359070fd9SAsad Kamal
49459070fd9SAsad Kamal /* Use TXCLK3 counter group for rx event */
49559070fd9SAsad Kamal /* Use TXCLK7 counter group for tx event */
49659070fd9SAsad Kamal /* Set the 2 events that we wish to watch, defined above */
49759070fd9SAsad Kamal /* 40 is event# for received msgs */
49859070fd9SAsad Kamal /* 2 is event# of posted requests sent */
49959070fd9SAsad Kamal perfctrrx = REG_SET_FIELD(perfctrrx, PCIE_PERF_CNTL_TXCLK3, EVENT0_SEL, 40);
50059070fd9SAsad Kamal perfctrtx = REG_SET_FIELD(perfctrtx, PCIE_PERF_CNTL_TXCLK7, EVENT0_SEL, 2);
50159070fd9SAsad Kamal
50259070fd9SAsad Kamal /* Write to enable desired perf counters */
50359070fd9SAsad Kamal WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx);
50459070fd9SAsad Kamal WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx);
50559070fd9SAsad Kamal
50659070fd9SAsad Kamal /* Zero out and enable SHADOW_WR
50759070fd9SAsad Kamal * Write 0x6:
50859070fd9SAsad Kamal * Bit 1 = Global Shadow wr(1)
50959070fd9SAsad Kamal * Bit 2 = Global counter reset enable(1)
51059070fd9SAsad Kamal */
51159070fd9SAsad Kamal WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
51259070fd9SAsad Kamal
51359070fd9SAsad Kamal /* Enable Gloabl Counter
51459070fd9SAsad Kamal * Write 0x1:
51559070fd9SAsad Kamal * Bit 0 = Global Counter Enable(1)
51659070fd9SAsad Kamal */
51759070fd9SAsad Kamal WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001);
51859070fd9SAsad Kamal
51959070fd9SAsad Kamal msleep(1000);
52059070fd9SAsad Kamal
52159070fd9SAsad Kamal /* Disable Global Counter, Reset and enable SHADOW_WR
52259070fd9SAsad Kamal * Write 0x6:
52359070fd9SAsad Kamal * Bit 1 = Global Shadow wr(1)
52459070fd9SAsad Kamal * Bit 2 = Global counter reset enable(1)
52559070fd9SAsad Kamal */
52659070fd9SAsad Kamal WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
52759070fd9SAsad Kamal
52859070fd9SAsad Kamal /* Get the upper and lower count */
52959070fd9SAsad Kamal *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) |
53059070fd9SAsad Kamal ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32);
53159070fd9SAsad Kamal *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) |
53259070fd9SAsad Kamal ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32);
53359070fd9SAsad Kamal }
53459070fd9SAsad Kamal
53539def24fSHawking Zhang const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
53639def24fSHawking Zhang .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
53739def24fSHawking Zhang .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
53839def24fSHawking Zhang .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
53939def24fSHawking Zhang .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
5400c552ed3SLe Ma .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
54139def24fSHawking Zhang .get_rev_id = nbio_v7_9_get_rev_id,
54239def24fSHawking Zhang .mc_access_enable = nbio_v7_9_mc_access_enable,
54339def24fSHawking Zhang .get_memsize = nbio_v7_9_get_memsize,
54439def24fSHawking Zhang .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
54539def24fSHawking Zhang .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
54639def24fSHawking Zhang .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
54739def24fSHawking Zhang .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
54839def24fSHawking Zhang .ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
54939def24fSHawking Zhang .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
55039def24fSHawking Zhang .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
55139def24fSHawking Zhang .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
55239def24fSHawking Zhang .get_clockgating_state = nbio_v7_9_get_clockgating_state,
55339def24fSHawking Zhang .ih_control = nbio_v7_9_ih_control,
55439def24fSHawking Zhang .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
55598a54e88SLe Ma .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
556ea2d2f8eSRajneesh Bhardwaj .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
55789fb3020SShiwu Zhang .init_registers = nbio_v7_9_init_registers,
55850709d18SLijo Lazar .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
55959070fd9SAsad Kamal .get_pcie_usage = nbio_v7_9_get_pcie_usage,
56039def24fSHawking Zhang };
5617692e1eeSTao Zhou
nbio_v7_9_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)5627692e1eeSTao Zhou static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
5637692e1eeSTao Zhou void *ras_error_status)
5647692e1eeSTao Zhou {
5657692e1eeSTao Zhou return;
5667692e1eeSTao Zhou }
5677692e1eeSTao Zhou
nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device * adev)5687692e1eeSTao Zhou static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
5697692e1eeSTao Zhou {
5707692e1eeSTao Zhou uint32_t bif_doorbell_intr_cntl;
5717692e1eeSTao Zhou struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
5727692e1eeSTao Zhou struct ras_err_data err_data = {0, 0, 0, NULL};
5737692e1eeSTao Zhou struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5747692e1eeSTao Zhou
5757692e1eeSTao Zhou bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
5767692e1eeSTao Zhou
5777692e1eeSTao Zhou if (REG_GET_FIELD(bif_doorbell_intr_cntl,
5787692e1eeSTao Zhou BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
5797692e1eeSTao Zhou /* driver has to clear the interrupt status when bif ring is disabled */
5807692e1eeSTao Zhou bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
5817692e1eeSTao Zhou BIF_BX0_BIF_DOORBELL_INT_CNTL,
5827692e1eeSTao Zhou RAS_CNTLR_INTERRUPT_CLEAR, 1);
5837692e1eeSTao Zhou WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
5847692e1eeSTao Zhou
5857692e1eeSTao Zhou if (!ras->disable_ras_err_cnt_harvest) {
5867692e1eeSTao Zhou /*
5877692e1eeSTao Zhou * clear error status after ras_controller_intr
5887692e1eeSTao Zhou * according to hw team and count ue number
5897692e1eeSTao Zhou * for query
5907692e1eeSTao Zhou */
5917692e1eeSTao Zhou nbio_v7_9_query_ras_error_count(adev, &err_data);
5927692e1eeSTao Zhou
5937692e1eeSTao Zhou /* logging on error cnt and printing for awareness */
5947692e1eeSTao Zhou obj->err_data.ue_count += err_data.ue_count;
5957692e1eeSTao Zhou obj->err_data.ce_count += err_data.ce_count;
5967692e1eeSTao Zhou
5977692e1eeSTao Zhou if (err_data.ce_count)
5987692e1eeSTao Zhou dev_info(adev->dev, "%ld correctable hardware "
5997692e1eeSTao Zhou "errors detected in %s block, "
6007692e1eeSTao Zhou "no user action is needed.\n",
6017692e1eeSTao Zhou obj->err_data.ce_count,
6027692e1eeSTao Zhou get_ras_block_str(adev->nbio.ras_if));
6037692e1eeSTao Zhou
6047692e1eeSTao Zhou if (err_data.ue_count)
6057692e1eeSTao Zhou dev_info(adev->dev, "%ld uncorrectable hardware "
6067692e1eeSTao Zhou "errors detected in %s block\n",
6077692e1eeSTao Zhou obj->err_data.ue_count,
6087692e1eeSTao Zhou get_ras_block_str(adev->nbio.ras_if));
6097692e1eeSTao Zhou }
6107692e1eeSTao Zhou
6117692e1eeSTao Zhou dev_info(adev->dev, "RAS controller interrupt triggered "
6127692e1eeSTao Zhou "by NBIF error\n");
6137692e1eeSTao Zhou }
6147692e1eeSTao Zhou }
6157692e1eeSTao Zhou
nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device * adev)6167692e1eeSTao Zhou static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
6177692e1eeSTao Zhou {
6187692e1eeSTao Zhou uint32_t bif_doorbell_intr_cntl;
6197692e1eeSTao Zhou
6207692e1eeSTao Zhou bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
6217692e1eeSTao Zhou
6227692e1eeSTao Zhou if (REG_GET_FIELD(bif_doorbell_intr_cntl,
6237692e1eeSTao Zhou BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
6247692e1eeSTao Zhou /* driver has to clear the interrupt status when bif ring is disabled */
6257692e1eeSTao Zhou bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
6267692e1eeSTao Zhou BIF_BX0_BIF_DOORBELL_INT_CNTL,
6277692e1eeSTao Zhou RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
6287692e1eeSTao Zhou
6297692e1eeSTao Zhou WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
6307692e1eeSTao Zhou
6317692e1eeSTao Zhou amdgpu_ras_global_ras_isr(adev);
6327692e1eeSTao Zhou }
6337692e1eeSTao Zhou }
6347692e1eeSTao Zhou
nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)6357692e1eeSTao Zhou static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
6367692e1eeSTao Zhou struct amdgpu_irq_src *src,
6377692e1eeSTao Zhou unsigned type,
6387692e1eeSTao Zhou enum amdgpu_interrupt_state state)
6397692e1eeSTao Zhou {
6407692e1eeSTao Zhou /* Dummy function, there is no initialization operation in driver */
6417692e1eeSTao Zhou
6427692e1eeSTao Zhou return 0;
6437692e1eeSTao Zhou }
6447692e1eeSTao Zhou
nbio_v7_9_process_ras_controller_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6457692e1eeSTao Zhou static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
6467692e1eeSTao Zhou struct amdgpu_irq_src *source,
6477692e1eeSTao Zhou struct amdgpu_iv_entry *entry)
6487692e1eeSTao Zhou {
6497692e1eeSTao Zhou /* By design, the ih cookie for ras_controller_irq should be written
6507692e1eeSTao Zhou * to BIFring instead of general iv ring. However, due to known bif ring
6517692e1eeSTao Zhou * hw bug, it has to be disabled. There is no chance the process function
6527692e1eeSTao Zhou * will be involked. Just left it as a dummy one.
6537692e1eeSTao Zhou */
6547692e1eeSTao Zhou return 0;
6557692e1eeSTao Zhou }
6567692e1eeSTao Zhou
nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)6577692e1eeSTao Zhou static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
6587692e1eeSTao Zhou struct amdgpu_irq_src *src,
6597692e1eeSTao Zhou unsigned type,
6607692e1eeSTao Zhou enum amdgpu_interrupt_state state)
6617692e1eeSTao Zhou {
6627692e1eeSTao Zhou /* Dummy function, there is no initialization operation in driver */
6637692e1eeSTao Zhou
6647692e1eeSTao Zhou return 0;
6657692e1eeSTao Zhou }
6667692e1eeSTao Zhou
nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6677692e1eeSTao Zhou static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
6687692e1eeSTao Zhou struct amdgpu_irq_src *source,
6697692e1eeSTao Zhou struct amdgpu_iv_entry *entry)
6707692e1eeSTao Zhou {
6717692e1eeSTao Zhou /* By design, the ih cookie for err_event_athub_irq should be written
6727692e1eeSTao Zhou * to BIFring instead of general iv ring. However, due to known bif ring
6737692e1eeSTao Zhou * hw bug, it has to be disabled. There is no chance the process function
6747692e1eeSTao Zhou * will be involked. Just left it as a dummy one.
6757692e1eeSTao Zhou */
6767692e1eeSTao Zhou return 0;
6777692e1eeSTao Zhou }
6787692e1eeSTao Zhou
6797692e1eeSTao Zhou static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
6807692e1eeSTao Zhou .set = nbio_v7_9_set_ras_controller_irq_state,
6817692e1eeSTao Zhou .process = nbio_v7_9_process_ras_controller_irq,
6827692e1eeSTao Zhou };
6837692e1eeSTao Zhou
6847692e1eeSTao Zhou static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
6857692e1eeSTao Zhou .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
6867692e1eeSTao Zhou .process = nbio_v7_9_process_err_event_athub_irq,
6877692e1eeSTao Zhou };
6887692e1eeSTao Zhou
nbio_v7_9_init_ras_controller_interrupt(struct amdgpu_device * adev)6897692e1eeSTao Zhou static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev)
6907692e1eeSTao Zhou {
6917692e1eeSTao Zhou int r;
6927692e1eeSTao Zhou
6937692e1eeSTao Zhou /* init the irq funcs */
6947692e1eeSTao Zhou adev->nbio.ras_controller_irq.funcs =
6957692e1eeSTao Zhou &nbio_v7_9_ras_controller_irq_funcs;
6967692e1eeSTao Zhou adev->nbio.ras_controller_irq.num_types = 1;
6977692e1eeSTao Zhou
6987692e1eeSTao Zhou /* register ras controller interrupt */
6997692e1eeSTao Zhou r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
7007692e1eeSTao Zhou NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
7017692e1eeSTao Zhou &adev->nbio.ras_controller_irq);
7027692e1eeSTao Zhou
7037692e1eeSTao Zhou return r;
7047692e1eeSTao Zhou }
7057692e1eeSTao Zhou
nbio_v7_9_init_ras_err_event_athub_interrupt(struct amdgpu_device * adev)7067692e1eeSTao Zhou static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
7077692e1eeSTao Zhou {
7087692e1eeSTao Zhou
7097692e1eeSTao Zhou int r;
7107692e1eeSTao Zhou
7117692e1eeSTao Zhou /* init the irq funcs */
7127692e1eeSTao Zhou adev->nbio.ras_err_event_athub_irq.funcs =
7137692e1eeSTao Zhou &nbio_v7_9_ras_err_event_athub_irq_funcs;
7147692e1eeSTao Zhou adev->nbio.ras_err_event_athub_irq.num_types = 1;
7157692e1eeSTao Zhou
7167692e1eeSTao Zhou /* register ras err event athub interrupt */
7177692e1eeSTao Zhou r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
7187692e1eeSTao Zhou NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
7197692e1eeSTao Zhou &adev->nbio.ras_err_event_athub_irq);
7207692e1eeSTao Zhou
7217692e1eeSTao Zhou return r;
7227692e1eeSTao Zhou }
7237692e1eeSTao Zhou
7247692e1eeSTao Zhou const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = {
7257692e1eeSTao Zhou .query_ras_error_count = nbio_v7_9_query_ras_error_count,
7267692e1eeSTao Zhou };
7277692e1eeSTao Zhou
7287692e1eeSTao Zhou struct amdgpu_nbio_ras nbio_v7_9_ras = {
7297692e1eeSTao Zhou .ras_block = {
7307692e1eeSTao Zhou .ras_comm = {
7317692e1eeSTao Zhou .name = "pcie_bif",
7327692e1eeSTao Zhou .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
7337692e1eeSTao Zhou .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
7347692e1eeSTao Zhou },
7357692e1eeSTao Zhou .hw_ops = &nbio_v7_9_ras_hw_ops,
7367692e1eeSTao Zhou .ras_late_init = amdgpu_nbio_ras_late_init,
7377692e1eeSTao Zhou },
7387692e1eeSTao Zhou .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring,
7397692e1eeSTao Zhou .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
7407692e1eeSTao Zhou .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt,
7417692e1eeSTao Zhou .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt,
7427692e1eeSTao Zhou };
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