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Searched refs:UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2710 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2706 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro
H A Dvcn_2_6_0_sh_mask.h63 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3768 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4014 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4049 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK … macro