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Searched refs:UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h203 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK … macro
H A Duvd_4_0_sh_mask.h744 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L macro
H A Duvd_4_2_sh_mask.h105 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 macro
H A Duvd_3_1_sh_mask.h105 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 macro
H A Duvd_6_0_sh_mask.h105 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 macro
H A Duvd_5_0_sh_mask.h105 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h425 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK … macro