Searched refs:UCR1_RRDYEN (Results 1 – 4 of 4) sorted by relevance
68 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ macro
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro397 ucr1 |= UCR1_RRDYEN; in imx_uart_start_rx()485 ucr1 &= ~UCR1_RRDYEN; in imx_uart_stop_rx_with_loopback_ctrl()1013 if ((ucr1 & UCR1_RRDYEN) == 0) in imx_uart_int()1505 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()1557 ucr1 |= UCR1_RRDYEN; in imx_uart_startup()1620 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | in imx_uart_shutdown()1908 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()1917 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()2053 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()[all …]
28 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro
531 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro