1cd0bda20SJean-Christophe Dubois /* 2cd0bda20SJean-Christophe Dubois * Device model for i.MX UART 3cd0bda20SJean-Christophe Dubois * 4cd0bda20SJean-Christophe Dubois * Copyright (c) 2008 OKL 5cd0bda20SJean-Christophe Dubois * Originally Written by Hans Jiang 6cd0bda20SJean-Christophe Dubois * Copyright (c) 2011 NICTA Pty Ltd. 7cd0bda20SJean-Christophe Dubois * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8cd0bda20SJean-Christophe Dubois * 9cd0bda20SJean-Christophe Dubois * This program is free software; you can redistribute it and/or 10cd0bda20SJean-Christophe Dubois * modify it under the terms of the GNU General Public License 11cd0bda20SJean-Christophe Dubois * as published by the Free Software Foundation; either version 12cd0bda20SJean-Christophe Dubois * 2 of the License, or (at your option) any later version. 13cd0bda20SJean-Christophe Dubois * 14cd0bda20SJean-Christophe Dubois * You should have received a copy of the GNU General Public License along 15cd0bda20SJean-Christophe Dubois * with this program; if not, see <http://www.gnu.org/licenses/>. 16cd0bda20SJean-Christophe Dubois */ 17cd0bda20SJean-Christophe Dubois 18cd0bda20SJean-Christophe Dubois #ifndef IMX_SERIAL_H 19cd0bda20SJean-Christophe Dubois #define IMX_SERIAL_H 20cd0bda20SJean-Christophe Dubois 21cd0bda20SJean-Christophe Dubois #include "hw/sysbus.h" 224d43a603SMarc-André Lureau #include "chardev/char-fe.h" 23db1015e9SEduardo Habkost #include "qom/object.h" 24*988f2442SRayhan Faizel #include "qemu/fifo32.h" 25cd0bda20SJean-Christophe Dubois 26cd0bda20SJean-Christophe Dubois #define TYPE_IMX_SERIAL "imx.serial" 278063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) 28cd0bda20SJean-Christophe Dubois 29*988f2442SRayhan Faizel #define FIFO_SIZE 32 30*988f2442SRayhan Faizel 31cd0bda20SJean-Christophe Dubois #define URXD_CHARRDY (1<<15) /* character read is valid */ 32cd0bda20SJean-Christophe Dubois #define URXD_ERR (1<<14) /* Character has error */ 33*988f2442SRayhan Faizel #define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */ 34478a573aSTrent Piepho #define URXD_FRMERR (1<<12) /* Character has frame error */ 35cd0bda20SJean-Christophe Dubois #define URXD_BRK (1<<11) /* Break received */ 36cd0bda20SJean-Christophe Dubois 37cd0bda20SJean-Christophe Dubois #define USR1_PARTYER (1<<15) /* Parity Error */ 38cd0bda20SJean-Christophe Dubois #define USR1_RTSS (1<<14) /* RTS pin status */ 39cd0bda20SJean-Christophe Dubois #define USR1_TRDY (1<<13) /* Tx ready */ 40cd0bda20SJean-Christophe Dubois #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ 41cd0bda20SJean-Christophe Dubois #define USR1_ESCF (1<<11) /* Escape sequence interrupt */ 42cd0bda20SJean-Christophe Dubois #define USR1_FRAMERR (1<<10) /* Framing error */ 43cd0bda20SJean-Christophe Dubois #define USR1_RRDY (1<<9) /* receiver ready */ 44cd0bda20SJean-Christophe Dubois #define USR1_AGTIM (1<<8) /* Aging timer interrupt */ 45cd0bda20SJean-Christophe Dubois #define USR1_DTRD (1<<7) /* DTR changed */ 46cd0bda20SJean-Christophe Dubois #define USR1_RXDS (1<<6) /* Receiver is idle */ 47cd0bda20SJean-Christophe Dubois #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ 48cd0bda20SJean-Christophe Dubois #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ 49cd0bda20SJean-Christophe Dubois 50cd0bda20SJean-Christophe Dubois #define USR2_ADET (1<<15) /* Autobaud complete */ 51cd0bda20SJean-Christophe Dubois #define USR2_TXFE (1<<14) /* Transmit FIFO empty */ 52cd0bda20SJean-Christophe Dubois #define USR2_DTRF (1<<13) /* DTR/DSR transition */ 53cd0bda20SJean-Christophe Dubois #define USR2_IDLE (1<<12) /* UART has been idle for too long */ 54cd0bda20SJean-Christophe Dubois #define USR2_ACST (1<<11) /* Autobaud counter stopped */ 55cd0bda20SJean-Christophe Dubois #define USR2_RIDELT (1<<10) /* Ring Indicator delta */ 56cd0bda20SJean-Christophe Dubois #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 57cd0bda20SJean-Christophe Dubois #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ 58cd0bda20SJean-Christophe Dubois #define USR2_WAKE (1<<7) /* Start bit detected */ 59cd0bda20SJean-Christophe Dubois #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ 60cd0bda20SJean-Christophe Dubois #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 61cd0bda20SJean-Christophe Dubois #define USR2_RTSF (1<<4) /* RTS transition */ 62cd0bda20SJean-Christophe Dubois #define USR2_TXDC (1<<3) /* Transmission complete */ 63cd0bda20SJean-Christophe Dubois #define USR2_BRCD (1<<2) /* Break condition detected */ 64cd0bda20SJean-Christophe Dubois #define USR2_ORE (1<<1) /* Overrun error */ 65cd0bda20SJean-Christophe Dubois #define USR2_RDR (1<<0) /* Receive data ready */ 66cd0bda20SJean-Christophe Dubois 67cd0bda20SJean-Christophe Dubois #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ 68cd0bda20SJean-Christophe Dubois #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ 69cd0bda20SJean-Christophe Dubois #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ 70cd0bda20SJean-Christophe Dubois #define UCR1_UARTEN (1<<0) /* UART Enable */ 71cd0bda20SJean-Christophe Dubois 72*988f2442SRayhan Faizel #define UCR2_ATEN (1<<3) /* Ageing Timer Enable */ 73cd0bda20SJean-Christophe Dubois #define UCR2_TXEN (1<<2) /* Transmitter enable */ 74cd0bda20SJean-Christophe Dubois #define UCR2_RXEN (1<<1) /* Receiver enable */ 75cd0bda20SJean-Christophe Dubois #define UCR2_SRST (1<<0) /* Reset complete */ 76cd0bda20SJean-Christophe Dubois 773c54cf77SHans-Erik Floryd #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ 78*988f2442SRayhan Faizel #define UCR4_OREN BIT(1) /* Overrun interrupt enable */ 7946d3fb63SAndrey Smirnov #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ 80bd96e100SMartin Kaiser #define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ 8146d3fb63SAndrey Smirnov 82cd0bda20SJean-Christophe Dubois #define UTS1_TXEMPTY (1<<6) 83cd0bda20SJean-Christophe Dubois #define UTS1_RXEMPTY (1<<5) 84cd0bda20SJean-Christophe Dubois #define UTS1_TXFULL (1<<4) 85cd0bda20SJean-Christophe Dubois #define UTS1_RXFULL (1<<3) 86cd0bda20SJean-Christophe Dubois 87*988f2442SRayhan Faizel #define TL_MASK 0x3f 88*988f2442SRayhan Faizel 89*988f2442SRayhan Faizel /* Bit time in nanoseconds assuming maximum baud rate of 115200 */ 90*988f2442SRayhan Faizel #define BIT_TIME_NS 8681 91*988f2442SRayhan Faizel 92*988f2442SRayhan Faizel /* Assume 8 bits per character */ 93*988f2442SRayhan Faizel #define NUM_BITS 8 94*988f2442SRayhan Faizel 95*988f2442SRayhan Faizel /* Ageing timer triggers after 8 characters */ 96*988f2442SRayhan Faizel #define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS) 97*988f2442SRayhan Faizel 98db1015e9SEduardo Habkost struct IMXSerialState { 99cd0bda20SJean-Christophe Dubois /*< private >*/ 100cd0bda20SJean-Christophe Dubois SysBusDevice parent_obj; 101cd0bda20SJean-Christophe Dubois 102cd0bda20SJean-Christophe Dubois /*< public >*/ 103cd0bda20SJean-Christophe Dubois MemoryRegion iomem; 104*988f2442SRayhan Faizel QEMUTimer ageing_timer; 105*988f2442SRayhan Faizel Fifo32 rx_fifo; 106cd0bda20SJean-Christophe Dubois 107cd0bda20SJean-Christophe Dubois uint32_t usr1; 108cd0bda20SJean-Christophe Dubois uint32_t usr2; 109cd0bda20SJean-Christophe Dubois uint32_t ucr1; 110cd0bda20SJean-Christophe Dubois uint32_t ucr2; 111cd0bda20SJean-Christophe Dubois uint32_t uts1; 112cd0bda20SJean-Christophe Dubois 113cd0bda20SJean-Christophe Dubois /* 114cd0bda20SJean-Christophe Dubois * The registers below are implemented just so that the 115cd0bda20SJean-Christophe Dubois * guest OS sees what it has written 116cd0bda20SJean-Christophe Dubois */ 117cd0bda20SJean-Christophe Dubois uint32_t onems; 118cd0bda20SJean-Christophe Dubois uint32_t ufcr; 119cd0bda20SJean-Christophe Dubois uint32_t ubmr; 120cd0bda20SJean-Christophe Dubois uint32_t ubrc; 121cd0bda20SJean-Christophe Dubois uint32_t ucr3; 12246d3fb63SAndrey Smirnov uint32_t ucr4; 123cd0bda20SJean-Christophe Dubois 124cd0bda20SJean-Christophe Dubois qemu_irq irq; 125becdfa00SMarc-André Lureau CharBackend chr; 126db1015e9SEduardo Habkost }; 127cd0bda20SJean-Christophe Dubois 128cd0bda20SJean-Christophe Dubois #endif 129