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Searched refs:THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_11_0_2_sh_mask.h46 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT macro
H A Dthm_10_0_sh_mask.h127 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT macro
H A Dthm_9_0_sh_mask.h271 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT macro
H A Dthm_13_0_2_sh_mask.h279 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT macro
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_thermal.c214 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); in vega12_thermal_enable_alert()
H A Dvega20_thermal.c285 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); in vega20_thermal_enable_alert()
H A Dvega10_thermal.c450 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); in vega10_thermal_enable_alert()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h148 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 macro
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c1370 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); in smu_v11_0_set_irq_state()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c1299 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); in smu_v13_0_set_irq_state()