/openbmc/qemu/include/tcg/ |
H A D | tcg-cond.h | 51 TCG_COND_GE = 0 | 0 | 2 | 1, enumerator 123 case TCG_COND_GE: in tcg_high_cond()
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/openbmc/qemu/target/mips/tcg/ |
H A D | tx79_translate.c | 276 return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); in trans_PCGTB() 288 return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); in trans_PCGTH() 300 return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); in trans_PCGTW()
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H A D | mxu_translate.c | 2797 tcg_gen_brcondi_tl(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less); in gen_mxu_S32CPS() 2841 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_done_hi); in gen_mxu_D16CPS() 2848 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_not_less_lo); in gen_mxu_D16CPS() 3665 tcg_gen_brcondi_tl(TCG_COND_GE, t2, bits5, l_xra_only); in gen_mxu_s32extr() 3717 tcg_gen_brcond_tl(TCG_COND_GE, t2, t4, l_xra_only); in gen_mxu_s32extrv() 4310 tcg_gen_brcondi_tl(TCG_COND_GE, t2, 5, l_exit); in gen_mxu_S32ALN()
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H A D | translate.c | 2369 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith_imm() 2399 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith_imm() 2590 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith() 2623 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith() 2660 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith() 2691 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); in gen_arith() 4073 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); in gen_loongson_multimedia() 4093 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); in gen_loongson_multimedia() 4533 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); in gen_trap() 4751 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); in gen_compute_branch() [all …]
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H A D | nanomips_translate.c.inc | 1204 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 1209 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); 2359 cond = TCG_COND_GE; 2507 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 2531 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 2534 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
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/openbmc/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_branch.c.inc | 78 TRANS(bge, ALL, gen_rr_bc, TCG_COND_GE)
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/openbmc/qemu/target/hexagon/ |
H A D | gen_tcg.h | 971 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 973 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 1037 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV) 1039 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV)
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H A D | genptr.c | 1051 tcg_gen_brcondi_tl(TCG_COND_GE, shift_amt, 0, positive); in gen_asr_r_r_sat() 1073 tcg_gen_brcondi_tl(TCG_COND_GE, shift_amt, 0, positive); in gen_asl_r_r_sat() 1115 tcg_gen_brcondi_tl(TCG_COND_GE, offset, 0, label); in gen_insert_rp()
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/openbmc/qemu/target/alpha/ |
H A D | translate.c | 512 case TCG_COND_GE: in gen_fold_mzero() 1712 tcg_gen_movcond_i64(TCG_COND_GE, vc, va, load_zero(ctx), in translate_one() 2261 gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc); in translate_one() 2811 ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21); in translate_one() 2843 ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21); in translate_one()
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/openbmc/qemu/tcg/ |
H A D | tci.c | 211 case TCG_COND_GE: in tci_compare32() 259 case TCG_COND_GE: in tci_compare64() 1050 [TCG_COND_GE] = "ge", in str_c()
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H A D | optimize.c | 621 case TCG_COND_GE: in do_constant_folding_cond_32() 655 case TCG_COND_GE: in do_constant_folding_cond_64() 689 case TCG_COND_GE: in do_constant_folding_cond_eq() 1373 case TCG_COND_GE: in fold_brcond2() 2347 case TCG_COND_GE: in fold_setcond2()
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/openbmc/qemu/target/sh4/ |
H A D | translate.c | 730 tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc() 894 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc() 916 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc() 1353 tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
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/openbmc/qemu/target/tricore/ |
H A D | translate.c | 2970 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); in gen_compute_branch() 5177 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator() 5659 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5699 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5807 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5843 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5896 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 6128 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); in decode_rr_divide() 6157 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); in decode_rr_divide() 7996 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); in decode_sys_interrupts() [all …]
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/openbmc/qemu/target/arm/tcg/ |
H A D | translate-vfp.c | 367 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, frn, frm); in trans_VSEL() 373 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, dest, frm); in trans_VSEL() 398 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm); in trans_VSEL() 404 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm); in trans_VSEL()
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/openbmc/qemu/target/ppc/translate/ |
H A D | spe-impl.c.inc | 167 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); 183 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); 199 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
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/openbmc/qemu/target/hexagon/idef-parser/ |
H A D | idef-parser.y | 652 $$ = gen_bin_cmp(c, &@1, TCG_COND_GE, &$1, &$3);
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/openbmc/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 312 case TCG_COND_GE: 729 [TCG_COND_GE] = BC | BI(0, CR_LT) | BO_COND_FALSE, 745 [TCG_COND_GE] = ISEL | BC_(0, CR_LT) | 1, 1820 case TCG_COND_GE: 1968 case TCG_COND_GE: 2048 case TCG_COND_GE: 2180 [TCG_COND_GE ] = { CR_GT, CR_LT }, 2229 case TCG_COND_GE: 3949 case TCG_COND_GE:
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/openbmc/qemu/target/rx/ |
H A D | translate.c | 278 dc->cond = TCG_COND_GE; in psw_cond() 288 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; in psw_cond() 304 dc->cond = TCG_COND_GE; in psw_cond()
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/openbmc/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 364 [TCG_COND_GE] = COND_GE, 1455 case TCG_COND_GE: 2522 [TCG_COND_GE] = I3616_CMGE, 2529 [TCG_COND_GE] = I3611_CMGE, 2536 [TCG_COND_GE] = I3617_CMGE0, 2543 [TCG_COND_GE] = I3612_CMGE0,
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/openbmc/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 422 [TCG_COND_GE] = S390_CC_GE, 440 [TCG_COND_GE] = S390_CC_GE, 572 case TCG_COND_GE: 1310 case TCG_COND_GE: 1373 case TCG_COND_GE: 3061 case TCG_COND_GE:
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvi.c.inc | 108 case TCG_COND_GE: 216 return gen_branch(ctx, a, TCG_COND_GE);
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/openbmc/qemu/target/openrisc/ |
H A D | translate.c | 988 tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, in trans_l_sfges() 1051 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfgesi()
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/openbmc/qemu/target/xtensa/ |
H A D | translate.c | 2838 .par = (const uint32_t[]){TCG_COND_GE}, 2845 .par = (const uint32_t[]){TCG_COND_GE}, 2866 .par = (const uint32_t[]){TCG_COND_GE}, 3272 .par = (const uint32_t[]){TCG_COND_GE}, 6695 .par = (const uint32_t[]){TCG_COND_GE}, 7368 .par = (const uint32_t[]){TCG_COND_GE}, 7373 .par = (const uint32_t[]){TCG_COND_GE},
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/openbmc/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 776 [TCG_COND_GE] = { OPC_BGE, false }, 813 case TCG_COND_GE: /* -> LT */ 935 case TCG_COND_GE:
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/openbmc/qemu/tcg/arm/ |
H A D | tcg-target.c.inc | 244 [TCG_COND_GE] = COND_GE, 1256 case TCG_COND_GE: 2591 [TCG_COND_GE] = INSN_VCGE, 2599 [TCG_COND_GE] = INSN_VCGE0,
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