/openbmc/linux/drivers/clk/davinci/ |
H A D | pll-da850.c | 49 SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV); 50 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); 51 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); 52 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); 53 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); 54 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV); 55 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); 172 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED); 173 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0); 174 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
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H A D | pll-da830.c | 33 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); 34 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); 35 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); 36 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); 37 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); 38 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
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H A D | pll.h | 70 #define SYSCLK(i, n, p, w, f) \ macro
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/openbmc/u-boot/doc/ |
H A D | README.mpc85xxcds | 150 XXXX1000 == CCB:SYSCLK 8:1 151 XXXX1010 == CCB:SYSCLK 10:1 184 XXXX0000 == CCB:SYSCLK 16:1 186 XXXX0010 == CCB:SYSCLK 2:1 187 XXXX0011 == CCB:SYSCLK 3:1 188 XXXX0100 == CCB:SYSCLK 4:1 189 XXXX0101 == CCB:SYSCLK 5:1 190 XXXX0110 == CCB:SYSCLK 6:1 192 XXXX1000 == CCB:SYSCLK 8:1 193 XXXX1001 == CCB:SYSCLK 9:1 [all …]
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/openbmc/u-boot/board/freescale/mpc8610hpcd/ |
H A D | README | 50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
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/openbmc/u-boot/board/freescale/mpc8641hpcn/ |
H A D | README | 30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz 31 001 :: SYSCLK = 40MHz 167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
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/openbmc/u-boot/board/freescale/mpc8544ds/ |
H A D | README | 68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | microchip,clock.h | 14 #define SYSCLK 3 macro
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | qoriq-clock.txt | 4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using 64 - clock-frequency: Input system clock frequency (SYSCLK)
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/openbmc/u-boot/board/freescale/mpc8572ds/ |
H A D | README | 62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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/openbmc/u-boot/board/freescale/bsc9132qds/ |
H A D | README | 75 (SYSCLK = 100MHz, DDRCLK = 100MHz) 77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
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/openbmc/linux/Documentation/sound/soc/ |
H A D | platform.rst | 62 4. SYSCLK configuration
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H A D | clocking.rst | 13 or SYSCLK). This audio master clock can be derived from a number of sources
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H A D | dai.rst | 31 (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
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/openbmc/u-boot/board/freescale/t4qds/ |
H A D | README | 54 Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) 58 System and DDR clock (SYSCLK, “DDRCLK”)
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/openbmc/u-boot/board/sbc8548/ |
H A D | README | 37 to reflect a different CCB:SYSCLK ratio] 246 D15 SYSCLK 66MHz 33MHz
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/openbmc/u-boot/board/freescale/t104xrdb/ |
H A D | README | 115 - System and DDR clock (SYSCLK, “DDRCLK”) 147 - System and DDR clock (SYSCLK, “DDRCLK”)
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/openbmc/u-boot/board/freescale/ls1021atwr/ |
H A D | README | 88 - System and DDR clock (SYSCLK, DDRCLK)
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/openbmc/u-boot/board/freescale/ls1021aqds/ |
H A D | README | 89 - System and DDR clock (SYSCLK, DDRCLK)
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/openbmc/u-boot/board/freescale/t102xqds/ |
H A D | README | 109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). 113 - System and DDR clock (SYSCLK, DDRCLK).
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/openbmc/u-boot/board/avionic-design/common/ |
H A D | pinmux-config-tamonten-ng.h | 259 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), 260 DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
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/openbmc/u-boot/board/freescale/t1040qds/ |
H A D | README | 74 - System and DDR clock (SYSCLK, “DDRCLK”)
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | integratorap.dts | 119 * SYSCLK clocks PCIv3 bridge, system controller and the
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/openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
H A D | pinmux.c | 230 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
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/openbmc/u-boot/board/nvidia/dalmore/ |
H A D | pinmux-config-dalmore.h | 220 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
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