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Searched refs:SYSCLK (Results 1 – 25 of 32) sorted by relevance

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/openbmc/linux/drivers/clk/davinci/
H A Dpll-da850.c49 SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
50 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
51 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
52 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
53 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
54 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
55 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
172 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
173 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
174 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
H A Dpll-da830.c33 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
34 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
35 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
36 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
37 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
38 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
H A Dpll.h70 #define SYSCLK(i, n, p, w, f) \ macro
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
184 XXXX0000 == CCB:SYSCLK 16:1
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
[all …]
/openbmc/u-boot/board/freescale/mpc8610hpcd/
H A DREADME50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
31 001 :: SYSCLK = 40MHz
167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/board/freescale/mpc8544ds/
H A DREADME68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmicrochip,clock.h14 #define SYSCLK 3 macro
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqoriq-clock.txt4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
64 - clock-frequency: Input system clock frequency (SYSCLK)
/openbmc/u-boot/board/freescale/mpc8572ds/
H A DREADME62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/openbmc/linux/Documentation/sound/soc/
H A Dplatform.rst62 4. SYSCLK configuration
H A Dclocking.rst13 or SYSCLK). This audio master clock can be derived from a number of sources
H A Ddai.rst31 (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
/openbmc/u-boot/board/freescale/t4qds/
H A DREADME54 Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
58 System and DDR clock (SYSCLK, “DDRCLK”)
/openbmc/u-boot/board/sbc8548/
H A DREADME37 to reflect a different CCB:SYSCLK ratio]
246 D15 SYSCLK 66MHz 33MHz
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME115 - System and DDR clock (SYSCLK, “DDRCLK”)
147 - System and DDR clock (SYSCLK, “DDRCLK”)
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME88 - System and DDR clock (SYSCLK, DDRCLK)
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME89 - System and DDR clock (SYSCLK, DDRCLK)
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
113 - System and DDR clock (SYSCLK, DDRCLK).
/openbmc/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h259 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
260 DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME74 - System and DDR clock (SYSCLK, “DDRCLK”)
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts119 * SYSCLK clocks PCIv3 bridge, system controller and the
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dpinmux.c230 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/openbmc/u-boot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h220 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),

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