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Searched refs:SW3 (Results 1 – 25 of 52) sorted by relevance

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/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB66 SW3[1:8]= 10010000
73 SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
74 SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
76 SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
153 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
157 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
162 Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
168 set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
175 set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME18 SW3 1111 0010
25 SW3 1111 0010
32 SW3 1111 0010
91 SW3 to SW12 are identical for all boot source
93 SW3 0010 0100
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds134 SW3=11101111
142 frequency can be changed by setting SW3:
146 SW3=XX00XXXX == CORE:CCB 2:1
159 SW3=00001000
173 SW3=11001000 (8X) (2:1)
176 SW3=X000XXXX == CORE:CCB 4:1
H A DREADME.b4860qds124 SW3 OFF OFF OFF ON OFF OFF ON OFF
136 SW3 [1:4] = 0001
140 SW3 [1:4] = 1000.
149 SW3 OFF OFF OFF ON OFF OFF ON OFF
161 SW3 [1:4] = 0001
165 SW3 [1:4] = 1000.
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
202 via DIP-switch: set SW3[5:7] = '100'
205 via DIP-switch: set SW3[5:7] = '100'
210 via DIP-Switch: set SW3[5:7] = '000'
213 via DIP-switch: set SW3[5:7] = '000'
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
250 SW3[3] = '1' for SD card(or 'switch sd' by software)
251 SW3[3] = '0' for eMMC (or 'switch emmc' by software)
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME288 SW3: 11100001
293 SW3: 11110001
298 SW3: 11100001
303 SW3: 11100001
310 SW3: 11100001
315 SW3: 11110001
320 SW3: 11100001
325 SW3: 11100001
/openbmc/u-boot/board/sbc8548/
H A DREADME216 SW3.1 CFG_HOST_AGT0 1* 0
217 SW3.2 CFG_HOST_AGT1 1* 0
218 SW3.3 CFG_HOST_AGT2 1* 0
219 SW3.4 CFG_IO_PORTS0 1* 0
220 SW3.5 CFG_IO_PORTS0 1 0*
221 SW3.6 CFG_IO_PORTS0 1 0*
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
97 SW3 {
/openbmc/linux/Documentation/hid/
H A Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME143 SW3[1:8] = '11100001'
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
159 via DIP-switch: set SW3[5:7] = '100'
163 via DIP-Switch: set SW3[5:7] = '000'
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
/openbmc/u-boot/board/phytec/pfla02/
H A DREADME21 The dip switch "SW3" on the board let choose the boot device.
/openbmc/u-boot/board/liebherr/display5/
H A Ddisplay5.c52 #define SW3 IMX_GPIO_NR(2, 7) macro
63 SW0, SW1, SW2, SW3
/openbmc/u-boot/include/power/
H A Dmc34vr500_pmic.h167 SW3, enumerator
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME17 SW3 is switch 18 as silk-screened onto the board.
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-clearfog-base.dts23 /* The rear SW3 button */
H A Darmada-388-clearfog.dts39 /* The rear SW3 button */
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt59 sw3 : regulator SW3 (register 29, bit 20)
88 sw3 : regulator SW3 (register 26, bit 0)
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME43 SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
/openbmc/linux/include/linux/mfd/
H A Dezx-pcap.h132 #define SW3 19 macro
/openbmc/linux/drivers/regulator/
H A Dcpcap-regulator.c336 CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
412 CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp-evk.dts123 sw3_reg: SW3 {
124 regulator-name = "SW3";
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dpm9g45.dts180 label = "SW3";
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Drzg2lc-smarc.dtsi148 * SW3 should be at position 2->3 so that SER0_RX line is activated
H A Drzg2l-smarc.dtsi139 * SW3 should be at position 2->3 so that SER0_RX line is activated
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-qsrb.dts59 regulator-name = "SW3";

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