1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2762161b0SHou Zhiqiang /* 3762161b0SHou Zhiqiang * Copyright 2016 Freescale Semiconductor, Inc. 4762161b0SHou Zhiqiang * Hou Zhiqiang <Zhiqiang.Hou@freescale.com> 5762161b0SHou Zhiqiang */ 6762161b0SHou Zhiqiang 7762161b0SHou Zhiqiang #ifndef __MC34VR500_H_ 8762161b0SHou Zhiqiang #define __MC34VR500_H_ 9762161b0SHou Zhiqiang 10762161b0SHou Zhiqiang #include <power/pmic.h> 11762161b0SHou Zhiqiang 12762161b0SHou Zhiqiang #define MC34VR500_I2C_ADDR 0x08 13762161b0SHou Zhiqiang 14762161b0SHou Zhiqiang /* Drivers name */ 15762161b0SHou Zhiqiang #define MC34VR500_REGULATOR_DRIVER "mc34vr500_regulator" 16762161b0SHou Zhiqiang 17762161b0SHou Zhiqiang /* Register map */ 18762161b0SHou Zhiqiang enum { 19762161b0SHou Zhiqiang MC34VR500_DEVICEID = 0x00, 20762161b0SHou Zhiqiang 21762161b0SHou Zhiqiang MC34VR500_SILICONREVID = 0x03, 22762161b0SHou Zhiqiang MC34VR500_FABID, 23762161b0SHou Zhiqiang MC34VR500_INTSTAT0, 24762161b0SHou Zhiqiang MC34VR500_INTMASK0, 25762161b0SHou Zhiqiang MC34VR500_INTSENSE0, 26762161b0SHou Zhiqiang MC34VR500_INTSTAT1, 27762161b0SHou Zhiqiang MC34VR500_INTMASK1, 28762161b0SHou Zhiqiang MC34VR500_INTSENSE1, 29762161b0SHou Zhiqiang 30762161b0SHou Zhiqiang MC34VR500_INTSTAT4 = 0x11, 31762161b0SHou Zhiqiang MC34VR500_INTMASK4, 32762161b0SHou Zhiqiang MC34VR500_INTSENSE4, 33762161b0SHou Zhiqiang 34762161b0SHou Zhiqiang MC34VR500_PWRCTL = 0x1B, 35762161b0SHou Zhiqiang 36762161b0SHou Zhiqiang MC34VR500_SW1VOLT = 0x2E, 37762161b0SHou Zhiqiang MC34VR500_SW1STBY, 38762161b0SHou Zhiqiang MC34VR500_SW1OFF, 39762161b0SHou Zhiqiang MC34VR500_SW1MODE, 40762161b0SHou Zhiqiang MC34VR500_SW1CONF, 41762161b0SHou Zhiqiang MC34VR500_SW2VOLT, 42762161b0SHou Zhiqiang MC34VR500_SW2STBY, 43762161b0SHou Zhiqiang MC34VR500_SW2OFF, 44762161b0SHou Zhiqiang MC34VR500_SW2MODE, 45762161b0SHou Zhiqiang MC34VR500_SW2CONF, 46762161b0SHou Zhiqiang 47762161b0SHou Zhiqiang MC34VR500_SW3VOLT = 0x3C, 48762161b0SHou Zhiqiang MC34VR500_SW3STBY, 49762161b0SHou Zhiqiang MC34VR500_SW3OFF, 50762161b0SHou Zhiqiang MC34VR500_SW3MODE, 51762161b0SHou Zhiqiang MC34VR500_SW3CONF, 52762161b0SHou Zhiqiang 53762161b0SHou Zhiqiang MC34VR500_SW4VOLT = 0x4A, 54762161b0SHou Zhiqiang MC34VR500_SW4STBY, 55762161b0SHou Zhiqiang MC34VR500_SW4OFF, 56762161b0SHou Zhiqiang MC34VR500_SW4MODE, 57762161b0SHou Zhiqiang MC34VR500_SW4CONF, 58762161b0SHou Zhiqiang 59762161b0SHou Zhiqiang MC34VR500_REFOUTCRTRL = 0x6A, 60762161b0SHou Zhiqiang 61762161b0SHou Zhiqiang MC34VR500_LDO1CTL = 0x6D, 62762161b0SHou Zhiqiang MC34VR500_LDO2CTL, 63762161b0SHou Zhiqiang MC34VR500_LDO3CTL, 64762161b0SHou Zhiqiang MC34VR500_LDO4CTL, 65762161b0SHou Zhiqiang MC34VR500_LDO5CTL, 66762161b0SHou Zhiqiang 67762161b0SHou Zhiqiang MC34VR500_PAGE_REGISTER = 0x7F, 68762161b0SHou Zhiqiang 69762161b0SHou Zhiqiang /* Internal RAM */ 70762161b0SHou Zhiqiang MC34VR500_SW1_VOLT = 0xA8, 71762161b0SHou Zhiqiang MC34VR500_SW1_SEQ, 72762161b0SHou Zhiqiang MC34VR500_SW1_CONFIG, 73762161b0SHou Zhiqiang 74762161b0SHou Zhiqiang MC34VR500_SW2_VOLT = 0xAC, 75762161b0SHou Zhiqiang MC34VR500_SW2_SEQ, 76762161b0SHou Zhiqiang MC34VR500_SW2_CONFIG, 77762161b0SHou Zhiqiang 78762161b0SHou Zhiqiang MC34VR500_SW3_VOLT = 0xB0, 79762161b0SHou Zhiqiang MC34VR500_SW3_SEQ, 80762161b0SHou Zhiqiang MC34VR500_SW3_CONFIG, 81762161b0SHou Zhiqiang 82762161b0SHou Zhiqiang MC34VR500_SW4_VOLT = 0xB8, 83762161b0SHou Zhiqiang MC34VR500_SW4_SEQ, 84762161b0SHou Zhiqiang MC34VR500_SW4_CONFIG, 85762161b0SHou Zhiqiang 86762161b0SHou Zhiqiang MC34VR500_REFOUT_SEQ = 0xC4, 87762161b0SHou Zhiqiang 88762161b0SHou Zhiqiang MC34VR500_LDO1_VOLT = 0xCC, 89762161b0SHou Zhiqiang MC34VR500_LDO1_SEQ, 90762161b0SHou Zhiqiang 91762161b0SHou Zhiqiang MC34VR500_LDO2_VOLT = 0xD0, 92762161b0SHou Zhiqiang MC34VR500_LDO2_SEQ, 93762161b0SHou Zhiqiang 94762161b0SHou Zhiqiang MC34VR500_LDO3_VOLT = 0xD4, 95762161b0SHou Zhiqiang MC34VR500_LDO3_SEQ, 96762161b0SHou Zhiqiang 97762161b0SHou Zhiqiang MC34VR500_LDO4_VOLT = 0xD8, 98762161b0SHou Zhiqiang MC34VR500_LDO4_SEQ, 99762161b0SHou Zhiqiang 100762161b0SHou Zhiqiang MC34VR500_LDO5_VOLT = 0xDC, 101762161b0SHou Zhiqiang MC34VR500_LDO5_SEQ, 102762161b0SHou Zhiqiang 103762161b0SHou Zhiqiang MC34VR500_PU_CONFIG1 = 0xE0, 104762161b0SHou Zhiqiang 105762161b0SHou Zhiqiang MC34VR500_TBB_POR = 0xE4, 106762161b0SHou Zhiqiang 107762161b0SHou Zhiqiang MC34VR500_PWRGD_EN = 0xE8, 108762161b0SHou Zhiqiang 109762161b0SHou Zhiqiang MC34VR500_NUM_OF_REGS, 110762161b0SHou Zhiqiang }; 111762161b0SHou Zhiqiang 112762161b0SHou Zhiqiang /* Registor offset based on SWxVOLT register */ 113762161b0SHou Zhiqiang #define MC34VR500_VOLT_OFFSET 0 114762161b0SHou Zhiqiang #define MC34VR500_STBY_OFFSET 1 115762161b0SHou Zhiqiang #define MC34VR500_OFF_OFFSET 2 116762161b0SHou Zhiqiang #define MC34VR500_MODE_OFFSET 3 117762161b0SHou Zhiqiang #define MC34VR500_CONF_OFFSET 4 118762161b0SHou Zhiqiang 119762161b0SHou Zhiqiang #define SW_MODE_MASK 0xf 120762161b0SHou Zhiqiang #define SW_MODE_SHIFT 0 121762161b0SHou Zhiqiang 122762161b0SHou Zhiqiang #define LDO_VOL_MASK 0xf 123762161b0SHou Zhiqiang #define LDO_EN (1 << 4) 124762161b0SHou Zhiqiang #define LDO_MODE_SHIFT 4 125762161b0SHou Zhiqiang #define LDO_MODE_MASK (1 << 4) 126762161b0SHou Zhiqiang #define LDO_MODE_OFF 0 127762161b0SHou Zhiqiang #define LDO_MODE_ON 1 128762161b0SHou Zhiqiang 129762161b0SHou Zhiqiang #define REFOUTEN (1 << 4) 130762161b0SHou Zhiqiang 131762161b0SHou Zhiqiang /* 132762161b0SHou Zhiqiang * Regulator Mode Control 133762161b0SHou Zhiqiang * 134762161b0SHou Zhiqiang * OFF: The regulator is switched off and the output voltage is discharged. 135762161b0SHou Zhiqiang * PFM: In this mode, the regulator is always in PFM mode, which is useful 136762161b0SHou Zhiqiang * at light loads for optimized efficiency. 137762161b0SHou Zhiqiang * PWM: In this mode, the regulator is always in PWM mode operation 138762161b0SHou Zhiqiang * regardless of load conditions. 139762161b0SHou Zhiqiang * APS: In this mode, the regulator moves automatically between pulse 140762161b0SHou Zhiqiang * skipping mode and PWM mode depending on load conditions. 141762161b0SHou Zhiqiang * 142762161b0SHou Zhiqiang * SWxMODE[3:0] 143762161b0SHou Zhiqiang * Normal Mode | Standby Mode | value 144762161b0SHou Zhiqiang * OFF OFF 0x0 145762161b0SHou Zhiqiang * PWM OFF 0x1 146762161b0SHou Zhiqiang * PFM OFF 0x3 147762161b0SHou Zhiqiang * APS OFF 0x4 148762161b0SHou Zhiqiang * PWM PWM 0x5 149762161b0SHou Zhiqiang * PWM APS 0x6 150762161b0SHou Zhiqiang * APS APS 0x8 151762161b0SHou Zhiqiang * APS PFM 0xc 152762161b0SHou Zhiqiang * PWM PFM 0xd 153762161b0SHou Zhiqiang */ 154762161b0SHou Zhiqiang #define OFF_OFF 0x0 155762161b0SHou Zhiqiang #define PWM_OFF 0x1 156762161b0SHou Zhiqiang #define PFM_OFF 0x3 157762161b0SHou Zhiqiang #define APS_OFF 0x4 158762161b0SHou Zhiqiang #define PWM_PWM 0x5 159762161b0SHou Zhiqiang #define PWM_APS 0x6 160762161b0SHou Zhiqiang #define APS_APS 0x8 161762161b0SHou Zhiqiang #define APS_PFM 0xc 162762161b0SHou Zhiqiang #define PWM_PFM 0xd 163762161b0SHou Zhiqiang 1644394ad12SHou Zhiqiang enum swx { 1654394ad12SHou Zhiqiang SW1 = 0, 1664394ad12SHou Zhiqiang SW2, 1674394ad12SHou Zhiqiang SW3, 1684394ad12SHou Zhiqiang SW4, 1694394ad12SHou Zhiqiang }; 1704394ad12SHou Zhiqiang 1714394ad12SHou Zhiqiang int mc34vr500_get_sw_volt(uint8_t sw); 1724394ad12SHou Zhiqiang int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt); 173762161b0SHou Zhiqiang int power_mc34vr500_init(unsigned char bus); 174762161b0SHou Zhiqiang #endif /* __MC34VR500_PMIC_H_ */ 175