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Searched refs:SPRN_HID0 (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S76 mfspr r0,SPRN_HID0
90 mfspr r0,SPRN_HID0
97 mtspr SPRN_HID0,r0
98 mfspr r0,SPRN_HID0
99 mfspr r0,SPRN_HID0
100 mfspr r0,SPRN_HID0
101 mfspr r0,SPRN_HID0
102 mfspr r0,SPRN_HID0
103 mfspr r0,SPRN_HID0
119 mfspr r3,SPRN_HID0
[all …]
H A Dl2cr_6xx.S116 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
119 mtspr SPRN_HID0,r4 /* Disable DPM */
432 mfspr r3,SPRN_HID0
434 mtspr SPRN_HID0,r3
447 mfspr r3,SPRN_HID0
451 mtspr SPRN_HID0,r3
453 mtspr SPRN_HID0,r3
H A Dcpu_setup_6xx.S96 mfspr r11,SPRN_HID0
103 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
105 mtspr SPRN_HID0,r11 /* enable caches */
115 mfspr r11,SPRN_HID0
121 mtspr SPRN_HID0,r11
187 mfspr r11,SPRN_HID0
201 mtspr SPRN_HID0,r11
260 mfspr r11,SPRN_HID0
285 mtspr SPRN_HID0,r11
356 mfspr r3,SPRN_HID0
[all …]
H A Didle_6xx.S31 mfspr r4,SPRN_HID0
33 mtspr SPRN_HID0, r4
120 mfspr r4,SPRN_HID0
130 mtspr SPRN_HID0,r4
164 mfspr r9,SPRN_HID0
H A Dpmc.c82 hid0 = mfspr(SPRN_HID0); in power4_enable_pmcs()
95 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0): in power4_enable_pmcs()
H A Didle_85xx.S59 mfspr r4,SPRN_HID0
63 mtspr SPRN_HID0,r4
H A Dmisc_32.S119 mfspr r5,SPRN_HID0
122 mtspr SPRN_HID0,r5
147 mfspr r5,SPRN_HID0
150 mtspr SPRN_HID0,r5
H A Dcpu_setup_e500.S250 mfspr r8,SPRN_HID0
252 mtspr SPRN_HID0,r9
272 mtspr SPRN_HID0,r8
/openbmc/linux/arch/powerpc/platforms/powermac/
H A Dcache.S56 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
59 mtspr SPRN_HID0,r4 /* Disable DPM */
85 mfspr r3,SPRN_HID0
87 mtspr SPRN_HID0,r3
93 mtspr SPRN_HID0,r3
95 mtspr SPRN_HID0,r3
167 mfspr r0,SPRN_HID0
169 mtspr SPRN_HID0,r0
175 mfspr r0,SPRN_HID0
177 mtspr SPRN_HID0,r0
[all …]
H A Dsleep.S224 mfspr r2,SPRN_HID0
229 mtspr SPRN_HID0,r2
258 mfspr r3,SPRN_HID0
261 mtspr SPRN_HID0,r3
/openbmc/linux/arch/powerpc/sysdev/
H A D6xx-suspend.S19 mfspr r5, SPRN_HID0
22 mtspr SPRN_HID0, r5
43 mfspr r5, SPRN_HID0
45 mtspr SPRN_HID0, r5
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c170 opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0); in update_hid_in_slw()
181 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); in update_power8_hid0()
193 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
200 hid0 = mfspr(SPRN_HID0); in unsplit_core()
205 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
237 hid0 = mfspr(SPRN_HID0); in split_core()
243 while (!(mfspr(SPRN_HID0) & split_parms[i].mask)) in split_core()
H A Dsubcore-asm.S60 1: mfspr r4, SPRN_HID0
H A Didle.c75 uint64_t hid0_val = mfspr(SPRN_HID0); in pnv_save_sprs_for_deep_states()
111 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_sleep.S38 mfspr r10, SPRN_HID0
41 mtspr SPRN_HID0, r10
54 mfspr r10, SPRN_HID0
58 mtspr SPRN_HID0, r10
H A Dlite5200_sleep.S96 mfspr r3, SPRN_HID0
100 mtspr SPRN_HID0, r3
231 mfspr r10, SPRN_HID0
233 mtspr SPRN_HID0, r5 /* invalidate caches */
235 mtspr SPRN_HID0, r10
240 mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
H A Dmpc52xx_pm.c153 hid0 = mfspr(SPRN_HID0); in mpc52xx_pm_enter()
154 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); in mpc52xx_pm_enter()
170 mtspr(SPRN_HID0, hid0); in mpc52xx_pm_enter()
/openbmc/linux/arch/powerpc/platforms/86xx/
H A Dcommon.c37 temp = mfspr(SPRN_HID0); in mpc86xx_time_init()
39 mtspr(SPRN_HID0, temp); in mpc86xx_time_init()
/openbmc/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_pm_ops.c37 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP; in mpc85xx_cpu_die()
38 mtspr(SPRN_HID0, tmp); in mpc85xx_cpu_die()
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S69 mfspr r5, SPRN_HID0
277 mfspr r3, SPRN_HID0
279 mtspr SPRN_HID0, r3
344 mfspr r5, SPRN_HID0
347 mtspr SPRN_HID0, r5
397 mtspr SPRN_HID0, r5
/openbmc/linux/arch/powerpc/platforms/cell/
H A Dras.c334 hid0 = mfspr(SPRN_HID0); in cbe_ras_init()
337 mtspr(SPRN_HID0, hid0); in cbe_ras_init()
/openbmc/linux/arch/powerpc/kvm/
H A De500_emulate.c256 case SPRN_HID0: in kvmppc_core_emulate_mtspr_e500()
384 case SPRN_HID0: in kvmppc_core_emulate_mfspr_e500()
H A Dbook3s_emulate.c711 case SPRN_HID0: in kvmppc_core_emulate_mtspr_pr()
897 case SPRN_HID0: in kvmppc_core_emulate_mfspr_pr()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h223 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ macro
625 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S44 mtspr SPRN_HID0,r3

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