Searched refs:SMU__NUM_MCLK_DPM_LEVELS (Results 1 – 18 of 18) sorted by relevance
27 #define SMU__NUM_MCLK_DPM_LEVELS 6 macro
42 #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
27 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro
30 #define SMU__NUM_MCLK_DPM_LEVELS 6 macro
235 …SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
32 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro62 #define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
91 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro106 #define SMU73_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
32 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro110 #define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
41 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro56 #define SMU75_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
33 #define SMU__NUM_MCLK_DPM_LEVELS 4 macro135 #define SMU74_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
179 …MU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
150 …MU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
166 …SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
179 …SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
192 …SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…