1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2013 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan #ifndef __KV_DPM_H__ 24*837d542aSEvan Quan #define __KV_DPM_H__ 25*837d542aSEvan Quan 26*837d542aSEvan Quan #define SMU__NUM_SCLK_DPM_STATE 8 27*837d542aSEvan Quan #define SMU__NUM_MCLK_DPM_LEVELS 4 28*837d542aSEvan Quan #define SMU__NUM_LCLK_DPM_LEVELS 8 29*837d542aSEvan Quan #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ 30*837d542aSEvan Quan #include "smu7_fusion.h" 31*837d542aSEvan Quan #include "ppsmc.h" 32*837d542aSEvan Quan 33*837d542aSEvan Quan #define SUMO_MAX_HARDWARE_POWERLEVELS 5 34*837d542aSEvan Quan 35*837d542aSEvan Quan #define SUMO_MAX_NUMBER_VOLTAGES 4 36*837d542aSEvan Quan 37*837d542aSEvan Quan struct sumo_vid_mapping_entry { 38*837d542aSEvan Quan u16 vid_2bit; 39*837d542aSEvan Quan u16 vid_7bit; 40*837d542aSEvan Quan }; 41*837d542aSEvan Quan 42*837d542aSEvan Quan struct sumo_vid_mapping_table { 43*837d542aSEvan Quan u32 num_entries; 44*837d542aSEvan Quan struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; 45*837d542aSEvan Quan }; 46*837d542aSEvan Quan 47*837d542aSEvan Quan struct sumo_sclk_voltage_mapping_entry { 48*837d542aSEvan Quan u32 sclk_frequency; 49*837d542aSEvan Quan u16 vid_2bit; 50*837d542aSEvan Quan u16 rsv; 51*837d542aSEvan Quan }; 52*837d542aSEvan Quan 53*837d542aSEvan Quan struct sumo_sclk_voltage_mapping_table { 54*837d542aSEvan Quan u32 num_max_dpm_entries; 55*837d542aSEvan Quan struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; 56*837d542aSEvan Quan }; 57*837d542aSEvan Quan 58*837d542aSEvan Quan #define TRINITY_AT_DFLT 30 59*837d542aSEvan Quan 60*837d542aSEvan Quan #define KV_NUM_NBPSTATES 4 61*837d542aSEvan Quan 62*837d542aSEvan Quan enum kv_pt_config_reg_type { 63*837d542aSEvan Quan KV_CONFIGREG_MMR = 0, 64*837d542aSEvan Quan KV_CONFIGREG_SMC_IND, 65*837d542aSEvan Quan KV_CONFIGREG_DIDT_IND, 66*837d542aSEvan Quan KV_CONFIGREG_CACHE, 67*837d542aSEvan Quan KV_CONFIGREG_MAX 68*837d542aSEvan Quan }; 69*837d542aSEvan Quan 70*837d542aSEvan Quan struct kv_pt_config_reg { 71*837d542aSEvan Quan u32 offset; 72*837d542aSEvan Quan u32 mask; 73*837d542aSEvan Quan u32 shift; 74*837d542aSEvan Quan u32 value; 75*837d542aSEvan Quan enum kv_pt_config_reg_type type; 76*837d542aSEvan Quan }; 77*837d542aSEvan Quan 78*837d542aSEvan Quan struct kv_lcac_config_values { 79*837d542aSEvan Quan u32 block_id; 80*837d542aSEvan Quan u32 signal_id; 81*837d542aSEvan Quan u32 t; 82*837d542aSEvan Quan }; 83*837d542aSEvan Quan 84*837d542aSEvan Quan struct kv_lcac_config_reg { 85*837d542aSEvan Quan u32 cntl; 86*837d542aSEvan Quan u32 block_mask; 87*837d542aSEvan Quan u32 block_shift; 88*837d542aSEvan Quan u32 signal_mask; 89*837d542aSEvan Quan u32 signal_shift; 90*837d542aSEvan Quan u32 t_mask; 91*837d542aSEvan Quan u32 t_shift; 92*837d542aSEvan Quan u32 enable_mask; 93*837d542aSEvan Quan u32 enable_shift; 94*837d542aSEvan Quan }; 95*837d542aSEvan Quan 96*837d542aSEvan Quan struct kv_pl { 97*837d542aSEvan Quan u32 sclk; 98*837d542aSEvan Quan u8 vddc_index; 99*837d542aSEvan Quan u8 ds_divider_index; 100*837d542aSEvan Quan u8 ss_divider_index; 101*837d542aSEvan Quan u8 allow_gnb_slow; 102*837d542aSEvan Quan u8 force_nbp_state; 103*837d542aSEvan Quan u8 display_wm; 104*837d542aSEvan Quan u8 vce_wm; 105*837d542aSEvan Quan }; 106*837d542aSEvan Quan 107*837d542aSEvan Quan struct kv_ps { 108*837d542aSEvan Quan struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 109*837d542aSEvan Quan u32 num_levels; 110*837d542aSEvan Quan bool need_dfs_bypass; 111*837d542aSEvan Quan u8 dpm0_pg_nb_ps_lo; 112*837d542aSEvan Quan u8 dpm0_pg_nb_ps_hi; 113*837d542aSEvan Quan u8 dpmx_nb_ps_lo; 114*837d542aSEvan Quan u8 dpmx_nb_ps_hi; 115*837d542aSEvan Quan }; 116*837d542aSEvan Quan 117*837d542aSEvan Quan struct kv_sys_info { 118*837d542aSEvan Quan u32 bootup_uma_clk; 119*837d542aSEvan Quan u32 bootup_sclk; 120*837d542aSEvan Quan u32 dentist_vco_freq; 121*837d542aSEvan Quan u32 nb_dpm_enable; 122*837d542aSEvan Quan u32 nbp_memory_clock[KV_NUM_NBPSTATES]; 123*837d542aSEvan Quan u32 nbp_n_clock[KV_NUM_NBPSTATES]; 124*837d542aSEvan Quan u16 bootup_nb_voltage_index; 125*837d542aSEvan Quan u8 htc_tmp_lmt; 126*837d542aSEvan Quan u8 htc_hyst_lmt; 127*837d542aSEvan Quan struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 128*837d542aSEvan Quan struct sumo_vid_mapping_table vid_mapping_table; 129*837d542aSEvan Quan u32 uma_channel_number; 130*837d542aSEvan Quan }; 131*837d542aSEvan Quan 132*837d542aSEvan Quan struct kv_power_info { 133*837d542aSEvan Quan u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 134*837d542aSEvan Quan u32 voltage_drop_t; 135*837d542aSEvan Quan struct kv_sys_info sys_info; 136*837d542aSEvan Quan struct kv_pl boot_pl; 137*837d542aSEvan Quan bool enable_nb_ps_policy; 138*837d542aSEvan Quan bool disable_nb_ps3_in_battery; 139*837d542aSEvan Quan bool video_start; 140*837d542aSEvan Quan bool battery_state; 141*837d542aSEvan Quan u32 lowest_valid; 142*837d542aSEvan Quan u32 highest_valid; 143*837d542aSEvan Quan u16 high_voltage_t; 144*837d542aSEvan Quan bool cac_enabled; 145*837d542aSEvan Quan bool bapm_enable; 146*837d542aSEvan Quan /* smc offsets */ 147*837d542aSEvan Quan u32 sram_end; 148*837d542aSEvan Quan u32 dpm_table_start; 149*837d542aSEvan Quan u32 soft_regs_start; 150*837d542aSEvan Quan /* dpm SMU tables */ 151*837d542aSEvan Quan u8 graphics_dpm_level_count; 152*837d542aSEvan Quan u8 uvd_level_count; 153*837d542aSEvan Quan u8 vce_level_count; 154*837d542aSEvan Quan u8 acp_level_count; 155*837d542aSEvan Quan u8 samu_level_count; 156*837d542aSEvan Quan u16 fps_high_t; 157*837d542aSEvan Quan SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; 158*837d542aSEvan Quan SMU7_Fusion_ACPILevel acpi_level; 159*837d542aSEvan Quan SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; 160*837d542aSEvan Quan SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; 161*837d542aSEvan Quan SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; 162*837d542aSEvan Quan SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; 163*837d542aSEvan Quan u8 uvd_boot_level; 164*837d542aSEvan Quan u8 vce_boot_level; 165*837d542aSEvan Quan u8 acp_boot_level; 166*837d542aSEvan Quan u8 samu_boot_level; 167*837d542aSEvan Quan u8 uvd_interval; 168*837d542aSEvan Quan u8 vce_interval; 169*837d542aSEvan Quan u8 acp_interval; 170*837d542aSEvan Quan u8 samu_interval; 171*837d542aSEvan Quan u8 graphics_boot_level; 172*837d542aSEvan Quan u8 graphics_interval; 173*837d542aSEvan Quan u8 graphics_therm_throttle_enable; 174*837d542aSEvan Quan u8 graphics_voltage_change_enable; 175*837d542aSEvan Quan u8 graphics_clk_slow_enable; 176*837d542aSEvan Quan u8 graphics_clk_slow_divider; 177*837d542aSEvan Quan u8 fps_low_t; 178*837d542aSEvan Quan u32 low_sclk_interrupt_t; 179*837d542aSEvan Quan bool uvd_power_gated; 180*837d542aSEvan Quan bool vce_power_gated; 181*837d542aSEvan Quan bool acp_power_gated; 182*837d542aSEvan Quan bool samu_power_gated; 183*837d542aSEvan Quan bool nb_dpm_enabled; 184*837d542aSEvan Quan /* flags */ 185*837d542aSEvan Quan bool enable_didt; 186*837d542aSEvan Quan bool enable_dpm; 187*837d542aSEvan Quan bool enable_auto_thermal_throttling; 188*837d542aSEvan Quan bool enable_nb_dpm; 189*837d542aSEvan Quan /* caps */ 190*837d542aSEvan Quan bool caps_cac; 191*837d542aSEvan Quan bool caps_power_containment; 192*837d542aSEvan Quan bool caps_sq_ramping; 193*837d542aSEvan Quan bool caps_db_ramping; 194*837d542aSEvan Quan bool caps_td_ramping; 195*837d542aSEvan Quan bool caps_tcp_ramping; 196*837d542aSEvan Quan bool caps_sclk_throttle_low_notification; 197*837d542aSEvan Quan bool caps_fps; 198*837d542aSEvan Quan bool caps_uvd_dpm; 199*837d542aSEvan Quan bool caps_uvd_pg; 200*837d542aSEvan Quan bool caps_vce_pg; 201*837d542aSEvan Quan bool caps_samu_pg; 202*837d542aSEvan Quan bool caps_acp_pg; 203*837d542aSEvan Quan bool caps_stable_p_state; 204*837d542aSEvan Quan bool caps_enable_dfs_bypass; 205*837d542aSEvan Quan bool caps_sclk_ds; 206*837d542aSEvan Quan struct amdgpu_ps current_rps; 207*837d542aSEvan Quan struct kv_ps current_ps; 208*837d542aSEvan Quan struct amdgpu_ps requested_rps; 209*837d542aSEvan Quan struct kv_ps requested_ps; 210*837d542aSEvan Quan }; 211*837d542aSEvan Quan 212*837d542aSEvan Quan /* XXX are these ok? */ 213*837d542aSEvan Quan #define KV_TEMP_RANGE_MIN (90 * 1000) 214*837d542aSEvan Quan #define KV_TEMP_RANGE_MAX (120 * 1000) 215*837d542aSEvan Quan 216*837d542aSEvan Quan /* kv_smc.c */ 217*837d542aSEvan Quan int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id); 218*837d542aSEvan Quan int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask); 219*837d542aSEvan Quan int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 220*837d542aSEvan Quan PPSMC_Msg msg, u32 parameter); 221*837d542aSEvan Quan int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 222*837d542aSEvan Quan u32 *value, u32 limit); 223*837d542aSEvan Quan int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable); 224*837d542aSEvan Quan int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable); 225*837d542aSEvan Quan int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev, 226*837d542aSEvan Quan u32 smc_start_address, 227*837d542aSEvan Quan const u8 *src, u32 byte_count, u32 limit); 228*837d542aSEvan Quan 229*837d542aSEvan Quan #endif 230