141a524abSAlex Deucher /* 241a524abSAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 341a524abSAlex Deucher * 441a524abSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 541a524abSAlex Deucher * copy of this software and associated documentation files (the "Software"), 641a524abSAlex Deucher * to deal in the Software without restriction, including without limitation 741a524abSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 841a524abSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 941a524abSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1041a524abSAlex Deucher * 1141a524abSAlex Deucher * The above copyright notice and this permission notice shall be included in 1241a524abSAlex Deucher * all copies or substantial portions of the Software. 1341a524abSAlex Deucher * 1441a524abSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1541a524abSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1641a524abSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1741a524abSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1841a524abSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1941a524abSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2041a524abSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2141a524abSAlex Deucher * 2241a524abSAlex Deucher */ 2341a524abSAlex Deucher #ifndef __KV_DPM_H__ 2441a524abSAlex Deucher #define __KV_DPM_H__ 2541a524abSAlex Deucher 2641a524abSAlex Deucher #define SMU__NUM_SCLK_DPM_STATE 8 2741a524abSAlex Deucher #define SMU__NUM_MCLK_DPM_LEVELS 4 2841a524abSAlex Deucher #define SMU__NUM_LCLK_DPM_LEVELS 8 2941a524abSAlex Deucher #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ 3041a524abSAlex Deucher #include "smu7_fusion.h" 3141a524abSAlex Deucher #include "trinity_dpm.h" 3241a524abSAlex Deucher #include "ppsmc.h" 3341a524abSAlex Deucher 3441a524abSAlex Deucher #define KV_NUM_NBPSTATES 4 3541a524abSAlex Deucher 3641a524abSAlex Deucher enum kv_pt_config_reg_type { 3741a524abSAlex Deucher KV_CONFIGREG_MMR = 0, 3841a524abSAlex Deucher KV_CONFIGREG_SMC_IND, 3941a524abSAlex Deucher KV_CONFIGREG_DIDT_IND, 4041a524abSAlex Deucher KV_CONFIGREG_CACHE, 4141a524abSAlex Deucher KV_CONFIGREG_MAX 4241a524abSAlex Deucher }; 4341a524abSAlex Deucher 4441a524abSAlex Deucher struct kv_pt_config_reg { 4541a524abSAlex Deucher u32 offset; 4641a524abSAlex Deucher u32 mask; 4741a524abSAlex Deucher u32 shift; 4841a524abSAlex Deucher u32 value; 4941a524abSAlex Deucher enum kv_pt_config_reg_type type; 5041a524abSAlex Deucher }; 5141a524abSAlex Deucher 5241a524abSAlex Deucher struct kv_lcac_config_values { 5341a524abSAlex Deucher u32 block_id; 5441a524abSAlex Deucher u32 signal_id; 5541a524abSAlex Deucher u32 t; 5641a524abSAlex Deucher }; 5741a524abSAlex Deucher 5841a524abSAlex Deucher struct kv_lcac_config_reg { 5941a524abSAlex Deucher u32 cntl; 6041a524abSAlex Deucher u32 block_mask; 6141a524abSAlex Deucher u32 block_shift; 6241a524abSAlex Deucher u32 signal_mask; 6341a524abSAlex Deucher u32 signal_shift; 6441a524abSAlex Deucher u32 t_mask; 6541a524abSAlex Deucher u32 t_shift; 6641a524abSAlex Deucher u32 enable_mask; 6741a524abSAlex Deucher u32 enable_shift; 6841a524abSAlex Deucher }; 6941a524abSAlex Deucher 7041a524abSAlex Deucher struct kv_pl { 7141a524abSAlex Deucher u32 sclk; 7241a524abSAlex Deucher u8 vddc_index; 7341a524abSAlex Deucher u8 ds_divider_index; 7441a524abSAlex Deucher u8 ss_divider_index; 7541a524abSAlex Deucher u8 allow_gnb_slow; 7641a524abSAlex Deucher u8 force_nbp_state; 7741a524abSAlex Deucher u8 display_wm; 7841a524abSAlex Deucher u8 vce_wm; 7941a524abSAlex Deucher }; 8041a524abSAlex Deucher 8141a524abSAlex Deucher struct kv_ps { 8241a524abSAlex Deucher struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 8341a524abSAlex Deucher u32 num_levels; 8441a524abSAlex Deucher bool need_dfs_bypass; 8541a524abSAlex Deucher u8 dpm0_pg_nb_ps_lo; 8641a524abSAlex Deucher u8 dpm0_pg_nb_ps_hi; 8741a524abSAlex Deucher u8 dpmx_nb_ps_lo; 8841a524abSAlex Deucher u8 dpmx_nb_ps_hi; 8941a524abSAlex Deucher }; 9041a524abSAlex Deucher 9141a524abSAlex Deucher struct kv_sys_info { 9241a524abSAlex Deucher u32 bootup_uma_clk; 9341a524abSAlex Deucher u32 bootup_sclk; 9441a524abSAlex Deucher u32 dentist_vco_freq; 9541a524abSAlex Deucher u32 nb_dpm_enable; 9641a524abSAlex Deucher u32 nbp_memory_clock[KV_NUM_NBPSTATES]; 9741a524abSAlex Deucher u32 nbp_n_clock[KV_NUM_NBPSTATES]; 9841a524abSAlex Deucher u16 bootup_nb_voltage_index; 9941a524abSAlex Deucher u8 htc_tmp_lmt; 10041a524abSAlex Deucher u8 htc_hyst_lmt; 10141a524abSAlex Deucher struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 10241a524abSAlex Deucher struct sumo_vid_mapping_table vid_mapping_table; 10341a524abSAlex Deucher u32 uma_channel_number; 10441a524abSAlex Deucher }; 10541a524abSAlex Deucher 10641a524abSAlex Deucher struct kv_power_info { 10741a524abSAlex Deucher u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 10841a524abSAlex Deucher u32 voltage_drop_t; 10941a524abSAlex Deucher struct kv_sys_info sys_info; 11041a524abSAlex Deucher struct kv_pl boot_pl; 11141a524abSAlex Deucher bool enable_nb_ps_policy; 11241a524abSAlex Deucher bool disable_nb_ps3_in_battery; 11341a524abSAlex Deucher bool video_start; 11441a524abSAlex Deucher bool battery_state; 11541a524abSAlex Deucher u32 lowest_valid; 11641a524abSAlex Deucher u32 highest_valid; 11741a524abSAlex Deucher u16 high_voltage_t; 11841a524abSAlex Deucher bool cac_enabled; 11941a524abSAlex Deucher bool bapm_enable; 12041a524abSAlex Deucher /* smc offsets */ 12141a524abSAlex Deucher u32 sram_end; 12241a524abSAlex Deucher u32 dpm_table_start; 12341a524abSAlex Deucher u32 soft_regs_start; 12441a524abSAlex Deucher /* dpm SMU tables */ 12541a524abSAlex Deucher u8 graphics_dpm_level_count; 12641a524abSAlex Deucher u8 uvd_level_count; 12741a524abSAlex Deucher u8 vce_level_count; 12841a524abSAlex Deucher u8 acp_level_count; 12941a524abSAlex Deucher u8 samu_level_count; 13041a524abSAlex Deucher u16 fps_high_t; 13141a524abSAlex Deucher SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; 13241a524abSAlex Deucher SMU7_Fusion_ACPILevel acpi_level; 13341a524abSAlex Deucher SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; 13441a524abSAlex Deucher SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; 13541a524abSAlex Deucher SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; 13641a524abSAlex Deucher SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; 13741a524abSAlex Deucher u8 uvd_boot_level; 13841a524abSAlex Deucher u8 vce_boot_level; 13941a524abSAlex Deucher u8 acp_boot_level; 14041a524abSAlex Deucher u8 samu_boot_level; 14141a524abSAlex Deucher u8 uvd_interval; 14241a524abSAlex Deucher u8 vce_interval; 14341a524abSAlex Deucher u8 acp_interval; 14441a524abSAlex Deucher u8 samu_interval; 14541a524abSAlex Deucher u8 graphics_boot_level; 14641a524abSAlex Deucher u8 graphics_interval; 14741a524abSAlex Deucher u8 graphics_therm_throttle_enable; 14841a524abSAlex Deucher u8 graphics_voltage_change_enable; 14941a524abSAlex Deucher u8 graphics_clk_slow_enable; 15041a524abSAlex Deucher u8 graphics_clk_slow_divider; 15141a524abSAlex Deucher u8 fps_low_t; 15241a524abSAlex Deucher u32 low_sclk_interrupt_t; 15341a524abSAlex Deucher bool uvd_power_gated; 15441a524abSAlex Deucher bool vce_power_gated; 15541a524abSAlex Deucher bool acp_power_gated; 15641a524abSAlex Deucher bool samu_power_gated; 15741a524abSAlex Deucher bool nb_dpm_enabled; 15841a524abSAlex Deucher /* flags */ 15941a524abSAlex Deucher bool enable_didt; 16041a524abSAlex Deucher bool enable_dpm; 16141a524abSAlex Deucher bool enable_auto_thermal_throttling; 16241a524abSAlex Deucher bool enable_nb_dpm; 16341a524abSAlex Deucher /* caps */ 16441a524abSAlex Deucher bool caps_cac; 16541a524abSAlex Deucher bool caps_power_containment; 16641a524abSAlex Deucher bool caps_sq_ramping; 16741a524abSAlex Deucher bool caps_db_ramping; 16841a524abSAlex Deucher bool caps_td_ramping; 16941a524abSAlex Deucher bool caps_tcp_ramping; 17041a524abSAlex Deucher bool caps_sclk_throttle_low_notification; 17141a524abSAlex Deucher bool caps_fps; 17241a524abSAlex Deucher bool caps_uvd_dpm; 17341a524abSAlex Deucher bool caps_uvd_pg; 17441a524abSAlex Deucher bool caps_vce_pg; 17541a524abSAlex Deucher bool caps_samu_pg; 17641a524abSAlex Deucher bool caps_acp_pg; 17741a524abSAlex Deucher bool caps_stable_p_state; 17841a524abSAlex Deucher bool caps_enable_dfs_bypass; 17941a524abSAlex Deucher bool caps_sclk_ds; 18041a524abSAlex Deucher struct radeon_ps current_rps; 18141a524abSAlex Deucher struct kv_ps current_ps; 18241a524abSAlex Deucher struct radeon_ps requested_rps; 18341a524abSAlex Deucher struct kv_ps requested_ps; 18441a524abSAlex Deucher }; 18541a524abSAlex Deucher 18641a524abSAlex Deucher 18741a524abSAlex Deucher /* kv_smc.c */ 18841a524abSAlex Deucher int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id); 18941a524abSAlex Deucher int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask); 19041a524abSAlex Deucher int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 19141a524abSAlex Deucher PPSMC_Msg msg, u32 parameter); 19241a524abSAlex Deucher int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 19341a524abSAlex Deucher u32 *value, u32 limit); 19441a524abSAlex Deucher int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable); 19564d03221SAlex Deucher int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable); 19641a524abSAlex Deucher int kv_copy_bytes_to_smc(struct radeon_device *rdev, 19741a524abSAlex Deucher u32 smc_start_address, 19841a524abSAlex Deucher const u8 *src, u32 byte_count, u32 limit); 19941a524abSAlex Deucher 20041a524abSAlex Deucher #endif 201