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Searched refs:SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_sh_mask.h2165 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
H A Dsdma0_4_2_sh_mask.h2155 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h1967 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h1943 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h2002 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro