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Searched refs:SCU_BASE (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dplatform.S33 #define SCU_BASE 0x1e6e2000 macro
34 #define SCU_PROT_KEY1 (SCU_BASE)
35 #define SCU_PROT_KEY2 (SCU_BASE + 0x010)
36 #define SCU_REV_ID (SCU_BASE + 0x014)
37 #define SCU_SYSRST_CTRL (SCU_BASE + 0x040)
38 #define SCU_SYSRST_CTRL_CLR (SCU_BASE + 0x044)
39 #define SCU_SYSRST_EVENT (SCU_BASE + 0x064)
40 #define SCU_CLK_STOP_CTRL_CLR (SCU_BASE + 0x084)
41 #define SCU_DEBUG_CTRL (SCU_BASE + 0x0c8)
42 #define SCU_DEBUG_CTRL2 (SCU_BASE + 0x0d8)
[all …]
H A Dspl.c20 #define SCU_BASE 0x1e6e2000 macro
21 #define SCU_SMP_SEC_ENTRY (SCU_BASE + 0x1bc)
22 #define SCU_WPROT2 (SCU_BASE + 0xf04)
H A Dboard_common.c132 #define SCU_BASE 0x1e6e2000 in board_add_ram_info() macro
138 if (readl(SCU_BASE + 0x594) & BIT(14)) in board_add_ram_info()
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c8 #define SCU_BASE 0x1e6e2000 macro
69 writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, in sgpio_init()
70 SCU_BASE | SCU_414); in sgpio_init()
78 reg = readl(SCU_BASE + 0x510); in espi_init()
129 reg = readl(SCU_BASE + 0x510); in acpi_init()
133 writel(reg, SCU_BASE + 0x510); in acpi_init()
135 reg = readl(SCU_BASE + 0x51c); in acpi_init()
137 writel(reg, SCU_BASE + 0x51c); in acpi_init()
141 reg = readl(SCU_BASE + 0x434); in acpi_init()
143 writel(reg, SCU_BASE + 0x434); in acpi_init()
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmactest.c592 setbits_le32(SCU_BASE + 0x410, BIT(4)); in scu_set_pinmux()
594 setbits_le32(SCU_BASE + 0x400, GENMASK(11, 0)); in scu_set_pinmux()
595 setbits_le32(SCU_BASE + 0x410, BIT(4)); in scu_set_pinmux()
596 clrbits_le32(SCU_BASE + 0x470, BIT(4)); in scu_set_pinmux()
600 setbits_le32(SCU_BASE + 0x400, GENMASK(23, 12)); in scu_set_pinmux()
601 setbits_le32(SCU_BASE + 0x410, BIT(5)); in scu_set_pinmux()
602 clrbits_le32(SCU_BASE + 0x470, BIT(5)); in scu_set_pinmux()
605 setbits_le32(SCU_BASE + 0x410, GENMASK(27, 16)); in scu_set_pinmux()
606 setbits_le32(SCU_BASE + 0x410, BIT(6)); in scu_set_pinmux()
607 clrbits_le32(SCU_BASE + 0x470, BIT(6)); in scu_set_pinmux()
[all …]
H A Dmem_io.h8 #define SCU_BASE 0x1e6e2000 macro
27 #define SCU_RD(offset) readl(SCU_BASE + offset)
28 #define SCU_WR(value, offset) writel(value, SCU_BASE + offset)
/openbmc/u-boot/board/aspeed/evb_ast2600/
H A Devb_ast2600.c8 #define SCU_BASE 0x1e6e2000 macro
69 writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, in sgpio_init()
70 SCU_BASE | SCU_414); in sgpio_init()
78 reg = readl(SCU_BASE + 0x510); in espi_init()
/openbmc/u-boot/board/aspeed/ast2600_intel/
H A Dintel.c9 #define SCU_BASE 0x1e6e2000 macro
10 #define SCU_PINMUX4 (SCU_BASE + 0x410)
12 #define SCU_PINMUX5 (SCU_BASE + 0x414)
17 #define SCU_GPIO_PD0 (SCU_BASE + 0x610)
19 #define SCU_PINMUX27 (SCU_BASE + 0x69c)