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Searched refs:SCLK_I2S2 (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3228-cru.h28 #define SCLK_I2S2 82 macro
H A Drk3188-cru-common.h33 #define SCLK_I2S2 77 macro
H A Drv1108-cru.h27 #define SCLK_I2S2 77 macro
H A Drk3328-cru.h31 #define SCLK_I2S2 43 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3188-cru-common.h33 #define SCLK_I2S2 77 macro
H A Drk3228-cru.h29 #define SCLK_I2S2 82 macro
H A Drv1108-cru.h27 #define SCLK_I2S2 77 macro
H A Dpx30-cru.h24 #define SCLK_I2S2 22 macro
H A Drk3328-cru.h32 #define SCLK_I2S2 43 macro
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3228.c447 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
H A Dclk-rk3328.c400 GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
H A Dclk-rv1108.c531 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
H A Dclk-rk3188.c555 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
H A Dclk-px30.c653 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
/openbmc/u-boot/arch/arm/dts/
H A Drk322x.dtsi161 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
H A Drk3328.dtsi158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
H A Drk322x.dtsi177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
H A Dpx30.dtsi430 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;