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Searched refs:RGMII (Results 1 – 25 of 176) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
103 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
109 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
H A Dxlnx,gmii-to-rgmii.yaml7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
H A Dadi,adin.yaml21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
H A Dmediatek-dwmac.yaml79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
112 1. tx clock will be inversed in MII/RGMII case,
122 1. rx clock will be inversed in MII/RGMII case.
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
H A Dingenic,mac.yaml44 description: RGMII receive clock delay defined in pico seconds
47 description: RGMII transmit clock delay defined in pico seconds
H A Dti,dp83869.yaml21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
24 conversions. The DP83869HM can also support Bridge Conversion from RGMII to
25 SGMII and SGMII to RGMII.
H A Dti,dp83867.yaml25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
H A Dethernet-controller.yaml81 # RGMII with internal RX and TX delays provided by the PHY,
85 # RGMII with internal RX delay provided by the PHY, the MAC
89 # RGMII with internal TX delay provided by the PHY, the MAC
278 RGMII Receive Clock Delay defined in pico seconds.This is used for
283 RGMII Transmit Clock Delay defined in pico seconds.This is used for
H A Dapm-xgene-enet.txt8 - "apm,xgene-enet": RGMII based 1G interface
42 - tx-delay: Delay value for RGMII bridge TX clock.
46 - rx-delay: Delay value for RGMII bridge RX clock.
/openbmc/linux/include/dt-bindings/phy/
H A Dphy-lan966x-serdes.h10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
31 - description: STG AXI/AHB or GMAC0 RGMII RX
39 - description: GMAC0 RGMII RX
H A Dstarfive,jh7110-syscrg.yaml23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
37 - description: GMAC1 RGMII RX
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dti,dp83867.txt5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmicrochip,lan966x-serdes.yaml14 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.
20 following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
/openbmc/u-boot/include/configs/
H A Dtqma6_mba6.h12 #define CONFIG_FEC_XCV_TYPE RGMII
H A Dzc5601.h23 #define CONFIG_FEC_XCV_TYPE RGMII
H A Dplatinum_titanium.h18 #define CONFIG_FEC_XCV_TYPE RGMII
H A Daristainetos2b.h21 #define CONFIG_FEC_XCV_TYPE RGMII
H A Daristainetos2.h21 #define CONFIG_FEC_XCV_TYPE RGMII
H A Dsecomx6quq7.h31 #define CONFIG_FEC_XCV_TYPE RGMII
H A Dmx6qarm2.h25 #define CONFIG_FEC_XCV_TYPE RGMII
H A Dsksimx6.h25 #define CONFIG_FEC_XCV_TYPE RGMII
/openbmc/u-boot/doc/
H A DREADME.fec_mxc12 RGMII selects 1000 Base-tx reduced pin count interface.
33 example if the CPU is connected directly via the RGMII interface to a
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME28 . eTSEC 1 supports RGMII/RMII
29 . eTSEC 2 supports RGMII
69 eTSEC1: Connected to RGMII PHY
70 eTSEC2: Connected to RGMII PHY

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