1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cf94a342SYe Li /* 3cf94a342SYe Li * Copyright 2014 Freescale Semiconductor, Inc. 4cf94a342SYe Li * 5cf94a342SYe Li * Configuration settings for the Freescale i.MX6SX Sabreauto board. 6cf94a342SYe Li */ 7cf94a342SYe Li 8cf94a342SYe Li #ifndef __CONFIG_H 9cf94a342SYe Li #define __CONFIG_H 10cf94a342SYe Li 11cf94a342SYe Li #include "mx6_common.h" 12cf94a342SYe Li 13cf94a342SYe Li /* Size of malloc() pool */ 14cf94a342SYe Li #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 15cf94a342SYe Li 16cf94a342SYe Li #define CONFIG_MXC_UART 17cf94a342SYe Li #define CONFIG_MXC_UART_BASE UART1_BASE 18cf94a342SYe Li 19cf94a342SYe Li #define CONFIG_EXTRA_ENV_SETTINGS \ 20cf94a342SYe Li "script=boot.scr\0" \ 21cf94a342SYe Li "image=zImage\0" \ 22cf94a342SYe Li "console=ttymxc0\0" \ 23cf94a342SYe Li "fdt_high=0xffffffff\0" \ 24cf94a342SYe Li "initrd_high=0xffffffff\0" \ 25cf94a342SYe Li "fdt_file=imx6sx-sabreauto.dtb\0" \ 26cf94a342SYe Li "fdt_addr=0x88000000\0" \ 27cf94a342SYe Li "boot_fdt=try\0" \ 28cf94a342SYe Li "ip_dyn=yes\0" \ 29cf94a342SYe Li "mmcdev=0\0" \ 30cf94a342SYe Li "mmcpart=1\0" \ 31cf94a342SYe Li "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 32cf94a342SYe Li "mmcargs=setenv bootargs console=${console},${baudrate} " \ 33cf94a342SYe Li "root=${mmcroot}\0" \ 34cf94a342SYe Li "loadbootscript=" \ 35cf94a342SYe Li "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 36cf94a342SYe Li "bootscript=echo Running bootscript from mmc ...; " \ 37cf94a342SYe Li "source\0" \ 38cf94a342SYe Li "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 39cf94a342SYe Li "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 40cf94a342SYe Li "mmcboot=echo Booting from mmc ...; " \ 41cf94a342SYe Li "run mmcargs; " \ 42cf94a342SYe Li "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 43cf94a342SYe Li "if run loadfdt; then " \ 44cf94a342SYe Li "bootz ${loadaddr} - ${fdt_addr}; " \ 45cf94a342SYe Li "else " \ 46cf94a342SYe Li "if test ${boot_fdt} = try; then " \ 47cf94a342SYe Li "bootz; " \ 48cf94a342SYe Li "else " \ 49cf94a342SYe Li "echo WARN: Cannot load the DT; " \ 50cf94a342SYe Li "fi; " \ 51cf94a342SYe Li "fi; " \ 52cf94a342SYe Li "else " \ 53cf94a342SYe Li "bootz; " \ 54cf94a342SYe Li "fi;\0" \ 55cf94a342SYe Li "netargs=setenv bootargs console=${console},${baudrate} " \ 56cf94a342SYe Li "root=/dev/nfs " \ 57cf94a342SYe Li "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 58cf94a342SYe Li "netboot=echo Booting from net ...; " \ 59cf94a342SYe Li "run netargs; " \ 60cf94a342SYe Li "if test ${ip_dyn} = yes; then " \ 61cf94a342SYe Li "setenv get_cmd dhcp; " \ 62cf94a342SYe Li "else " \ 63cf94a342SYe Li "setenv get_cmd tftp; " \ 64cf94a342SYe Li "fi; " \ 65cf94a342SYe Li "${get_cmd} ${image}; " \ 66cf94a342SYe Li "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 67cf94a342SYe Li "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 68cf94a342SYe Li "bootz ${loadaddr} - ${fdt_addr}; " \ 69cf94a342SYe Li "else " \ 70cf94a342SYe Li "if test ${boot_fdt} = try; then " \ 71cf94a342SYe Li "bootz; " \ 72cf94a342SYe Li "else " \ 73cf94a342SYe Li "echo WARN: Cannot load the DT; " \ 74cf94a342SYe Li "fi; " \ 75cf94a342SYe Li "fi; " \ 76cf94a342SYe Li "else " \ 77cf94a342SYe Li "bootz; " \ 78cf94a342SYe Li "fi;\0" 79cf94a342SYe Li 80cf94a342SYe Li #define CONFIG_BOOTCOMMAND \ 81cf94a342SYe Li "mmc dev ${mmcdev};" \ 82cf94a342SYe Li "mmc dev ${mmcdev}; if mmc rescan; then " \ 83cf94a342SYe Li "if run loadbootscript; then " \ 84cf94a342SYe Li "run bootscript; " \ 85cf94a342SYe Li "else " \ 86cf94a342SYe Li "if run loadimage; then " \ 87cf94a342SYe Li "run mmcboot; " \ 88cf94a342SYe Li "else run netboot; " \ 89cf94a342SYe Li "fi; " \ 90cf94a342SYe Li "fi; " \ 91cf94a342SYe Li "else run netboot; fi" 92cf94a342SYe Li 93cf94a342SYe Li /* Miscellaneous configurable options */ 94cf94a342SYe Li #define CONFIG_SYS_MEMTEST_START 0x80000000 95cf94a342SYe Li #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 96cf94a342SYe Li 97cf94a342SYe Li /* Physical Memory Map */ 98cf94a342SYe Li #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 99cf94a342SYe Li 100cf94a342SYe Li #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 101cf94a342SYe Li #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 102cf94a342SYe Li #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 103cf94a342SYe Li 104cf94a342SYe Li #define CONFIG_SYS_INIT_SP_OFFSET \ 105cf94a342SYe Li (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 106cf94a342SYe Li #define CONFIG_SYS_INIT_SP_ADDR \ 107cf94a342SYe Li (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 108cf94a342SYe Li 109cf94a342SYe Li /* MMC Configuration */ 110cf94a342SYe Li #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR 111cf94a342SYe Li 112cf94a342SYe Li /* I2C Configs */ 113cf94a342SYe Li #define CONFIG_SYS_I2C_MXC 114cf94a342SYe Li #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 115cf94a342SYe Li #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 116cf94a342SYe Li #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 117cf94a342SYe Li #define CONFIG_SYS_I2C_SPEED 100000 118cf94a342SYe Li 119cf94a342SYe Li /* NAND stuff */ 120cf94a342SYe Li #define CONFIG_SYS_MAX_NAND_DEVICE 1 121cf94a342SYe Li #define CONFIG_SYS_NAND_BASE 0x40000000 122cf94a342SYe Li #define CONFIG_SYS_NAND_5_ADDR_CYCLE 123cf94a342SYe Li #define CONFIG_SYS_NAND_ONFI_DETECTION 124cf94a342SYe Li 125cf94a342SYe Li /* DMA stuff, needed for GPMI/MXS NAND support */ 126cf94a342SYe Li 127cf94a342SYe Li /* Network */ 128cf94a342SYe Li 129cf94a342SYe Li #define CONFIG_FEC_MXC 130cf94a342SYe Li 131cf94a342SYe Li #define IMX_FEC_BASE ENET2_BASE_ADDR 132cf94a342SYe Li #define CONFIG_FEC_MXC_PHYADDR 0x0 133cf94a342SYe Li 134cf94a342SYe Li #define CONFIG_FEC_XCV_TYPE RGMII 135cf94a342SYe Li #define CONFIG_ETHPRIME "FEC" 136cf94a342SYe Li 137cf94a342SYe Li #define CONFIG_PHY_ATHEROS 138cf94a342SYe Li 139cf94a342SYe Li #ifdef CONFIG_CMD_USB 140cf94a342SYe Li #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 141cf94a342SYe Li #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 142cf94a342SYe Li #define CONFIG_MXC_USB_FLAGS 0 143cf94a342SYe Li #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 144cf94a342SYe Li #endif 145cf94a342SYe Li 146cf94a342SYe Li #define CONFIG_IMX_THERMAL 147cf94a342SYe Li 148cf94a342SYe Li #ifdef CONFIG_FSL_QSPI 149cf94a342SYe Li #define CONFIG_SYS_FSL_QSPI_AHB 150cf94a342SYe Li #define FSL_QSPI_FLASH_SIZE SZ_32M 151cf94a342SYe Li #define FSL_QSPI_FLASH_NUM 2 152cf94a342SYe Li #endif 153cf94a342SYe Li 154cf94a342SYe Li #define CONFIG_ENV_OFFSET (8 * SZ_64K) 155cf94a342SYe Li #define CONFIG_ENV_SIZE SZ_8K 156cf94a342SYe Li 157cf94a342SYe Li #define CONFIG_SYS_FSL_USDHC_NUM 2 158cf94a342SYe Li #if defined(CONFIG_ENV_IS_IN_MMC) 159cf94a342SYe Li #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ 160cf94a342SYe Li #endif 161cf94a342SYe Li 162cf94a342SYe Li #endif /* __CONFIG_H */ 163