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Searched refs:REG_WAIT (Results 1 – 25 of 51) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_hwseq.c60 REG_WAIT(DOMAIN1_PG_STATUS, in dcn302_dpp_pg_control()
68 REG_WAIT(DOMAIN3_PG_STATUS, in dcn302_dpp_pg_control()
76 REG_WAIT(DOMAIN5_PG_STATUS, in dcn302_dpp_pg_control()
84 REG_WAIT(DOMAIN7_PG_STATUS, in dcn302_dpp_pg_control()
92 REG_WAIT(DOMAIN9_PG_STATUS, in dcn302_dpp_pg_control()
117 REG_WAIT(DOMAIN0_PG_STATUS, in dcn302_hubp_pg_control()
125 REG_WAIT(DOMAIN2_PG_STATUS, in dcn302_hubp_pg_control()
133 REG_WAIT(DOMAIN4_PG_STATUS, in dcn302_hubp_pg_control()
141 REG_WAIT(DOMAIN6_PG_STATUS, in dcn302_hubp_pg_control()
149 REG_WAIT(DOMAIN8_PG_STATUS, in dcn302_hubp_pg_control()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.c91 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_dmcu_load_iram()
115 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_get_dmcu_psr_state()
139 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
233 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
310 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
341 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
363 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
413 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
431 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
[all …]
H A Ddce_abm.c66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
106 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
134 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
206 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
H A Ddce_aux.c146 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
157 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
221 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
350 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c333 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
348 REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
357 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
361 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
438 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc32_reset_fifo()
H A Ddcn32_optc.c165 REG_WAIT(OTG_CLOCK_CONTROL, in optc32_disable_crtc()
180 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc32_phantom_crtc_post_enable()
H A Ddcn32_hwseq.c92 REG_WAIT(DOMAIN16_PG_STATUS, in dcn32_dsc_pg_control()
100 REG_WAIT(DOMAIN17_PG_STATUS, in dcn32_dsc_pg_control()
108 REG_WAIT(DOMAIN18_PG_STATUS, in dcn32_dsc_pg_control()
116 REG_WAIT(DOMAIN19_PG_STATUS, in dcn32_dsc_pg_control()
174 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn32_hubp_pg_control()
178 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn32_hubp_pg_control()
182 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn32_hubp_pg_control()
186 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn32_hubp_pg_control()
H A Ddcn32_hubp.c102 REG_WAIT(DCHUBP_CNTL, in hubp32_phantom_hubp_post_enable()
H A Ddcn32_mmhubbub.c94 REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100); in mmhubbub32_warmup_mcif()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c73 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
81 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
107 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
112 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */ in dcn31_hpo_dp_stream_enc_dp_unblank()
121 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
126 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
153 REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_dp_blank()
H A Ddcn31_apg.c54 REG_WAIT(APG_CONTROL, in apg31_enable()
58 REG_WAIT(APG_CONTROL, in apg31_enable()
H A Ddcn31_hwseq.c304 REG_WAIT(DOMAIN16_PG_STATUS, in dcn31_dsc_pg_control()
312 REG_WAIT(DOMAIN17_PG_STATUS, in dcn31_dsc_pg_control()
320 REG_WAIT(DOMAIN18_PG_STATUS, in dcn31_dsc_pg_control()
456 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
460 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
464 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
468 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
H A Ddcn31_optc.c136 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_disable_crtc()
156 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_immediate_disable_crtc()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.c286 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
333 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
360 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
401 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_triplebuffer_lock()
H A Ddcn20_hwseq.c379 REG_WAIT(DOMAIN16_PG_STATUS, in dcn20_dsc_pg_control()
387 REG_WAIT(DOMAIN17_PG_STATUS, in dcn20_dsc_pg_control()
395 REG_WAIT(DOMAIN18_PG_STATUS, in dcn20_dsc_pg_control()
403 REG_WAIT(DOMAIN19_PG_STATUS, in dcn20_dsc_pg_control()
411 REG_WAIT(DOMAIN20_PG_STATUS, in dcn20_dsc_pg_control()
419 REG_WAIT(DOMAIN21_PG_STATUS, in dcn20_dsc_pg_control()
450 REG_WAIT(DOMAIN1_PG_STATUS, in dcn20_dpp_pg_control()
458 REG_WAIT(DOMAIN3_PG_STATUS, in dcn20_dpp_pg_control()
466 REG_WAIT(DOMAIN5_PG_STATUS, in dcn20_dpp_pg_control()
474 REG_WAIT(DOMAIN7_PG_STATUS, in dcn20_dpp_pg_control()
[all …]
H A Ddcn20_stream_encoder.c239 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc2_update_gsp7_128_info_packet()
516 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc2_stream_encoder_dp_unblank()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c58 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_triplebuffer_lock()
128 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_lock()
300 …REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdat… in optc3_wait_drr_doublebuffer_pending_clear()
H A Ddcn30_vpg.c72 REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, in vpg3_update_generic_info_packet()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c146 REG_WAIT(OTG_CLOCK_CONTROL, in optc314_disable_crtc()
161 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc314_phantom_crtc_post_enable()
H A Ddcn314_hwseq.c264 REG_WAIT(DOMAIN16_PG_STATUS, in dcn314_dsc_pg_control()
272 REG_WAIT(DOMAIN17_PG_STATUS, in dcn314_dsc_pg_control()
280 REG_WAIT(DOMAIN18_PG_STATUS, in dcn314_dsc_pg_control()
288 REG_WAIT(DOMAIN19_PG_STATUS, in dcn314_dsc_pg_control()
H A Ddcn314_dio_stream_encoder.c62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc314_reset_fifo()
342 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc314_stream_encoder_dp_unblank()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_update_generic_info_packet()
653 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in enc1_stream_encoder_set_throttled_vcp_size()
796 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
809 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_stream_encoder_send_immediate_sdp_message()
852 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
943 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
H A Ddcn10_optc.c486 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
494 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
565 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
675 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc1_lock()
833 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
839 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c182 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); in dcn20_update_clocks_update_dentist()
209 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); in dcn20_update_clocks_update_dentist()
212 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); in dcn20_update_clocks_update_dentist()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c58 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc201_triplebuffer_lock()

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