164b1d0e8SNicholas Kazlauskas /*
264b1d0e8SNicholas Kazlauskas * Copyright 2016 Advanced Micro Devices, Inc.
364b1d0e8SNicholas Kazlauskas *
464b1d0e8SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a
564b1d0e8SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"),
664b1d0e8SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation
764b1d0e8SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense,
864b1d0e8SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the
964b1d0e8SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions:
1064b1d0e8SNicholas Kazlauskas *
1164b1d0e8SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in
1264b1d0e8SNicholas Kazlauskas * all copies or substantial portions of the Software.
1364b1d0e8SNicholas Kazlauskas *
1464b1d0e8SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1564b1d0e8SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1664b1d0e8SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1764b1d0e8SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1864b1d0e8SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1964b1d0e8SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2064b1d0e8SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE.
2164b1d0e8SNicholas Kazlauskas *
2264b1d0e8SNicholas Kazlauskas * Authors: AMD
2364b1d0e8SNicholas Kazlauskas *
2464b1d0e8SNicholas Kazlauskas */
2564b1d0e8SNicholas Kazlauskas
2664b1d0e8SNicholas Kazlauskas
2764b1d0e8SNicholas Kazlauskas #include "dm_services.h"
2864b1d0e8SNicholas Kazlauskas #include "dm_helpers.h"
2964b1d0e8SNicholas Kazlauskas #include "core_types.h"
3064b1d0e8SNicholas Kazlauskas #include "resource.h"
3164b1d0e8SNicholas Kazlauskas #include "dccg.h"
3264b1d0e8SNicholas Kazlauskas #include "dce/dce_hwseq.h"
3364b1d0e8SNicholas Kazlauskas #include "clk_mgr.h"
3464b1d0e8SNicholas Kazlauskas #include "reg_helper.h"
3564b1d0e8SNicholas Kazlauskas #include "abm.h"
3664b1d0e8SNicholas Kazlauskas #include "hubp.h"
3764b1d0e8SNicholas Kazlauskas #include "dchubbub.h"
3864b1d0e8SNicholas Kazlauskas #include "timing_generator.h"
3964b1d0e8SNicholas Kazlauskas #include "opp.h"
4064b1d0e8SNicholas Kazlauskas #include "ipp.h"
4164b1d0e8SNicholas Kazlauskas #include "mpc.h"
4264b1d0e8SNicholas Kazlauskas #include "mcif_wb.h"
4364b1d0e8SNicholas Kazlauskas #include "dc_dmub_srv.h"
4464b1d0e8SNicholas Kazlauskas #include "dcn31_hwseq.h"
4564b1d0e8SNicholas Kazlauskas #include "link_hwss.h"
4664b1d0e8SNicholas Kazlauskas #include "dpcd_defs.h"
4764b1d0e8SNicholas Kazlauskas #include "dce/dmub_outbox.h"
48d5a43956SWenjing Liu #include "link.h"
4932f1d0cfSEric Yang #include "dcn10/dcn10_hw_sequencer.h"
500d4b4253SJimmy Kizito #include "inc/link_enc_cfg.h"
51fd8811e6SMichael Strauss #include "dcn30/dcn30_vpg.h"
525ffb5267SMichael Strauss #include "dce/dce_i2c_hw.h"
5364b1d0e8SNicholas Kazlauskas
5464b1d0e8SNicholas Kazlauskas #define DC_LOGGER_INIT(logger)
5564b1d0e8SNicholas Kazlauskas
5664b1d0e8SNicholas Kazlauskas #define CTX \
5764b1d0e8SNicholas Kazlauskas hws->ctx
5864b1d0e8SNicholas Kazlauskas #define REG(reg)\
5964b1d0e8SNicholas Kazlauskas hws->regs->reg
6064b1d0e8SNicholas Kazlauskas #define DC_LOGGER \
6164b1d0e8SNicholas Kazlauskas dc->ctx->logger
6264b1d0e8SNicholas Kazlauskas
6364b1d0e8SNicholas Kazlauskas
6464b1d0e8SNicholas Kazlauskas #undef FN
6564b1d0e8SNicholas Kazlauskas #define FN(reg_name, field_name) \
6664b1d0e8SNicholas Kazlauskas hws->shifts->field_name, hws->masks->field_name
6764b1d0e8SNicholas Kazlauskas
enable_memory_low_power(struct dc * dc)689959125aSJake Wang static void enable_memory_low_power(struct dc *dc)
699959125aSJake Wang {
709959125aSJake Wang struct dce_hwseq *hws = dc->hwseq;
719959125aSJake Wang int i;
729959125aSJake Wang
739959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.dmcu) {
749959125aSJake Wang // Force ERAM to shutdown if DMCU is not enabled
759959125aSJake Wang if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
769959125aSJake Wang REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
779959125aSJake Wang }
789959125aSJake Wang }
799959125aSJake Wang
809959125aSJake Wang // Set default OPTC memory power states
819959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.optc) {
829959125aSJake Wang // Shutdown when unassigned and light sleep in VBLANK
839959125aSJake Wang REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
849959125aSJake Wang }
859959125aSJake Wang
869959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.vga) {
879959125aSJake Wang // Power down VGA memory
889959125aSJake Wang REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
899959125aSJake Wang }
909959125aSJake Wang
916818f755SCharlene Liu if (dc->debug.enable_mem_low_power.bits.mpc &&
926818f755SCharlene Liu dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
939959125aSJake Wang dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
949959125aSJake Wang
959959125aSJake Wang
969959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
979959125aSJake Wang // Power down VPGs
989959125aSJake Wang for (i = 0; i < dc->res_pool->stream_enc_count; i++)
999959125aSJake Wang dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
1004652ae7aSHarry Wentland #if defined(CONFIG_DRM_AMD_DC_FP)
1019959125aSJake Wang for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
1029959125aSJake Wang dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
1039959125aSJake Wang #endif
1049959125aSJake Wang }
1059959125aSJake Wang
1069959125aSJake Wang }
1079959125aSJake Wang
dcn31_init_hw(struct dc * dc)10864b1d0e8SNicholas Kazlauskas void dcn31_init_hw(struct dc *dc)
10964b1d0e8SNicholas Kazlauskas {
11064b1d0e8SNicholas Kazlauskas struct abm **abms = dc->res_pool->multiple_abms;
11164b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq;
11264b1d0e8SNicholas Kazlauskas struct dc_bios *dcb = dc->ctx->dc_bios;
11364b1d0e8SNicholas Kazlauskas struct resource_pool *res_pool = dc->res_pool;
11464b1d0e8SNicholas Kazlauskas uint32_t backlight = MAX_BACKLIGHT_LEVEL;
115ebd1e719SLeo (Hanghong) Ma int i;
11664b1d0e8SNicholas Kazlauskas
11764b1d0e8SNicholas Kazlauskas if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
11864b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
11964b1d0e8SNicholas Kazlauskas
12064b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb)) {
12164b1d0e8SNicholas Kazlauskas hws->funcs.bios_golden_init(dc);
1226818f755SCharlene Liu if (hws->funcs.disable_vga)
12364b1d0e8SNicholas Kazlauskas hws->funcs.disable_vga(dc->hwseq);
12464b1d0e8SNicholas Kazlauskas }
125f2949a51SJake Wang // Initialize the dccg
126f2949a51SJake Wang if (res_pool->dccg->funcs->dccg_init)
127f2949a51SJake Wang res_pool->dccg->funcs->dccg_init(res_pool->dccg);
12864b1d0e8SNicholas Kazlauskas
1299959125aSJake Wang enable_memory_low_power(dc);
130fd8811e6SMichael Strauss
13164b1d0e8SNicholas Kazlauskas if (dc->ctx->dc_bios->fw_info_valid) {
13264b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz =
13364b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
13464b1d0e8SNicholas Kazlauskas
13564b1d0e8SNicholas Kazlauskas if (res_pool->dccg && res_pool->hubbub) {
13664b1d0e8SNicholas Kazlauskas
13764b1d0e8SNicholas Kazlauskas (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
13864b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
13964b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dccg_ref_clock_inKhz);
14064b1d0e8SNicholas Kazlauskas
14164b1d0e8SNicholas Kazlauskas (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
14264b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz,
14364b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dchub_ref_clock_inKhz);
14464b1d0e8SNicholas Kazlauskas } else {
14564b1d0e8SNicholas Kazlauskas // Not all ASICs have DCCG sw component
14664b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz =
14764b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz;
14864b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dchub_ref_clock_inKhz =
14964b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz;
15064b1d0e8SNicholas Kazlauskas }
15164b1d0e8SNicholas Kazlauskas } else
15264b1d0e8SNicholas Kazlauskas ASSERT_CRITICAL(false);
15364b1d0e8SNicholas Kazlauskas
15464b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) {
15564b1d0e8SNicholas Kazlauskas /* Power up AND update implementation according to the
15664b1d0e8SNicholas Kazlauskas * required signal (which may be different from the
15764b1d0e8SNicholas Kazlauskas * default signal on connector).
15864b1d0e8SNicholas Kazlauskas */
15964b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i];
16064b1d0e8SNicholas Kazlauskas
16164d283cbSJimmy Kizito if (link->ep_type != DISPLAY_ENDPOINT_PHY)
16264d283cbSJimmy Kizito continue;
16364d283cbSJimmy Kizito
16464b1d0e8SNicholas Kazlauskas link->link_enc->funcs->hw_init(link->link_enc);
16564b1d0e8SNicholas Kazlauskas
16664b1d0e8SNicholas Kazlauskas /* Check for enabled DIG to identify enabled display */
16764b1d0e8SNicholas Kazlauskas if (link->link_enc->funcs->is_dig_enabled &&
1685abef8e5SJingwen Zhu link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
16964b1d0e8SNicholas Kazlauskas link->link_status.link_active = true;
1705abef8e5SJingwen Zhu if (link->link_enc->funcs->fec_is_active &&
1715abef8e5SJingwen Zhu link->link_enc->funcs->fec_is_active(link->link_enc))
1725abef8e5SJingwen Zhu link->fec_state = dc_link_fec_enabled;
1735abef8e5SJingwen Zhu }
17464b1d0e8SNicholas Kazlauskas }
17564b1d0e8SNicholas Kazlauskas
17664b1d0e8SNicholas Kazlauskas /* we want to turn off all dp displays before doing detection */
17798ce7d32SWenjing Liu dc->link_srv->blank_all_dp_displays(dc);
17864b1d0e8SNicholas Kazlauskas
179384bd90dSRoman Li if (hws->funcs.enable_power_gating_plane)
180384bd90dSRoman Li hws->funcs.enable_power_gating_plane(dc->hwseq, true);
181384bd90dSRoman Li
18264b1d0e8SNicholas Kazlauskas /* If taking control over from VBIOS, we may want to optimize our first
18364b1d0e8SNicholas Kazlauskas * mode set, so we need to skip powering down pipes until we know which
18464b1d0e8SNicholas Kazlauskas * pipes we want to use.
18564b1d0e8SNicholas Kazlauskas * Otherwise, if taking control is not possible, we need to power
18664b1d0e8SNicholas Kazlauskas * everything down.
18764b1d0e8SNicholas Kazlauskas */
1887aba117aSJarif Aftab if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
1892d017189SDuncan Ma
1902d017189SDuncan Ma // we want to turn off edp displays if odm is enabled and no seamless boot
1912d017189SDuncan Ma if (!dc->caps.seamless_odm) {
1922d017189SDuncan Ma for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1932d017189SDuncan Ma struct timing_generator *tg = dc->res_pool->timing_generators[i];
1942d017189SDuncan Ma uint32_t num_opps, opp_id_src0, opp_id_src1;
1952d017189SDuncan Ma
1962d017189SDuncan Ma num_opps = 1;
1972d017189SDuncan Ma if (tg) {
1982d017189SDuncan Ma if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {
1992d017189SDuncan Ma tg->funcs->get_optc_source(tg, &num_opps,
2002d017189SDuncan Ma &opp_id_src0, &opp_id_src1);
2012d017189SDuncan Ma }
2022d017189SDuncan Ma }
2032d017189SDuncan Ma
2042d017189SDuncan Ma if (num_opps > 1) {
20598ce7d32SWenjing Liu dc->link_srv->blank_all_edp_displays(dc);
2062d017189SDuncan Ma break;
2072d017189SDuncan Ma }
2082d017189SDuncan Ma }
2092d017189SDuncan Ma }
2102d017189SDuncan Ma
21164b1d0e8SNicholas Kazlauskas hws->funcs.init_pipes(dc, dc->current_state);
21264b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
21364b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
21464b1d0e8SNicholas Kazlauskas !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
21564b1d0e8SNicholas Kazlauskas }
21664b1d0e8SNicholas Kazlauskas
21764b1d0e8SNicholas Kazlauskas for (i = 0; i < res_pool->audio_count; i++) {
21864b1d0e8SNicholas Kazlauskas struct audio *audio = res_pool->audios[i];
21964b1d0e8SNicholas Kazlauskas
22064b1d0e8SNicholas Kazlauskas audio->funcs->hw_init(audio);
22164b1d0e8SNicholas Kazlauskas }
22264b1d0e8SNicholas Kazlauskas
22364b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) {
22464b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i];
22564b1d0e8SNicholas Kazlauskas
22664b1d0e8SNicholas Kazlauskas if (link->panel_cntl)
22764b1d0e8SNicholas Kazlauskas backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
22864b1d0e8SNicholas Kazlauskas }
22964b1d0e8SNicholas Kazlauskas
23064b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->res_pool->pipe_count; i++) {
23164b1d0e8SNicholas Kazlauskas if (abms[i] != NULL)
23264b1d0e8SNicholas Kazlauskas abms[i]->funcs->abm_init(abms[i], backlight);
23364b1d0e8SNicholas Kazlauskas }
23464b1d0e8SNicholas Kazlauskas
23564b1d0e8SNicholas Kazlauskas /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
23664b1d0e8SNicholas Kazlauskas REG_WRITE(DIO_MEM_PWR_CTRL, 0);
23764b1d0e8SNicholas Kazlauskas
2385ffb5267SMichael Strauss // Set i2c to light sleep until engine is setup
2395ffb5267SMichael Strauss if (dc->debug.enable_mem_low_power.bits.i2c)
2405ffb5267SMichael Strauss REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
2415ffb5267SMichael Strauss
2420a068b68SJake Wang if (hws->funcs.setup_hpo_hw_control)
2430a068b68SJake Wang hws->funcs.setup_hpo_hw_control(hws, false);
2440a068b68SJake Wang
24564b1d0e8SNicholas Kazlauskas if (!dc->debug.disable_clock_gate) {
24664b1d0e8SNicholas Kazlauskas /* enable all DCN clock gating */
24764b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
24864b1d0e8SNicholas Kazlauskas
24964b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
25064b1d0e8SNicholas Kazlauskas
25164b1d0e8SNicholas Kazlauskas REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
25264b1d0e8SNicholas Kazlauskas }
25364b1d0e8SNicholas Kazlauskas
25464b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
25564b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
25664b1d0e8SNicholas Kazlauskas
25764b1d0e8SNicholas Kazlauskas if (dc->clk_mgr->funcs->notify_wm_ranges)
25864b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
25964b1d0e8SNicholas Kazlauskas
26037403cedSAyush Gupta if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
26164b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
26264b1d0e8SNicholas Kazlauskas
26364b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
26464b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->force_pstate_change_control(
26564b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub, false, false);
2664652ae7aSHarry Wentland #if defined(CONFIG_DRM_AMD_DC_FP)
26764b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->init_crb)
26864b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
2699fa0fb77SMeenakshikumar Somasundaram #endif
270d63e31f6SJosip Pavic
271d63e31f6SJosip Pavic // Get DMCUB capabilities
272e97cc04fSJosip Pavic dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
273d63e31f6SJosip Pavic dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
2744f63b7a5SAurabindo Pillai dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
27564b1d0e8SNicholas Kazlauskas }
27664b1d0e8SNicholas Kazlauskas
dcn31_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)27764b1d0e8SNicholas Kazlauskas void dcn31_dsc_pg_control(
27864b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws,
27964b1d0e8SNicholas Kazlauskas unsigned int dsc_inst,
28064b1d0e8SNicholas Kazlauskas bool power_on)
28164b1d0e8SNicholas Kazlauskas {
28264b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1;
28364b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2;
28464b1d0e8SNicholas Kazlauskas uint32_t org_ip_request_cntl = 0;
28564b1d0e8SNicholas Kazlauskas
28664b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_dsc_power_gate)
28764b1d0e8SNicholas Kazlauskas return;
28864b1d0e8SNicholas Kazlauskas
289e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
290e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
291e22ad7e3SJake Wang power_on)
292e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
293e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst);
294e22ad7e3SJake Wang
29564b1d0e8SNicholas Kazlauskas REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
29664b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0)
29764b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
29864b1d0e8SNicholas Kazlauskas
29964b1d0e8SNicholas Kazlauskas switch (dsc_inst) {
30064b1d0e8SNicholas Kazlauskas case 0: /* DSC0 */
30164b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG,
30264b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate);
30364b1d0e8SNicholas Kazlauskas
30464b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN16_PG_STATUS,
30564b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status,
30664b1d0e8SNicholas Kazlauskas 1, 1000);
30764b1d0e8SNicholas Kazlauskas break;
30864b1d0e8SNicholas Kazlauskas case 1: /* DSC1 */
30964b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG,
31064b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate);
31164b1d0e8SNicholas Kazlauskas
31264b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN17_PG_STATUS,
31364b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status,
31464b1d0e8SNicholas Kazlauskas 1, 1000);
31564b1d0e8SNicholas Kazlauskas break;
31664b1d0e8SNicholas Kazlauskas case 2: /* DSC2 */
31764b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG,
31864b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate);
31964b1d0e8SNicholas Kazlauskas
32064b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN18_PG_STATUS,
32164b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status,
32264b1d0e8SNicholas Kazlauskas 1, 1000);
32364b1d0e8SNicholas Kazlauskas break;
32464b1d0e8SNicholas Kazlauskas default:
32564b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER();
32664b1d0e8SNicholas Kazlauskas break;
32764b1d0e8SNicholas Kazlauskas }
32864b1d0e8SNicholas Kazlauskas
32964b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0)
33064b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
331e22ad7e3SJake Wang
332e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
333e22ad7e3SJake Wang if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
334e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
335e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst);
336e22ad7e3SJake Wang }
337e22ad7e3SJake Wang
33864b1d0e8SNicholas Kazlauskas }
33964b1d0e8SNicholas Kazlauskas
34064b1d0e8SNicholas Kazlauskas
dcn31_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)34164b1d0e8SNicholas Kazlauskas void dcn31_enable_power_gating_plane(
34264b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws,
34364b1d0e8SNicholas Kazlauskas bool enable)
34464b1d0e8SNicholas Kazlauskas {
34564b1d0e8SNicholas Kazlauskas bool force_on = true; /* disable power gating */
346a905f0b5SCharlene Liu uint32_t org_ip_request_cntl = 0;
34764b1d0e8SNicholas Kazlauskas
3488639bd70SCharlene Liu if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
34964b1d0e8SNicholas Kazlauskas force_on = false;
35064b1d0e8SNicholas Kazlauskas
351a905f0b5SCharlene Liu REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
352a905f0b5SCharlene Liu if (org_ip_request_cntl == 0)
353a905f0b5SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
35464b1d0e8SNicholas Kazlauskas /* DCHUBP0/1/2/3/4/5 */
35564b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
35664b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
35764b1d0e8SNicholas Kazlauskas /* DPP0/1/2/3/4/5 */
35864b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
35964b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
3608639bd70SCharlene Liu
3618639bd70SCharlene Liu force_on = true; /* disable power gating */
3628639bd70SCharlene Liu if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
3638639bd70SCharlene Liu force_on = false;
36464b1d0e8SNicholas Kazlauskas
36564b1d0e8SNicholas Kazlauskas /* DCS0/1/2/3/4/5 */
36664b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
36764b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
36864b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
369a905f0b5SCharlene Liu
370a905f0b5SCharlene Liu if (org_ip_request_cntl == 0)
371a905f0b5SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
37264b1d0e8SNicholas Kazlauskas }
37364b1d0e8SNicholas Kazlauskas
dcn31_update_info_frame(struct pipe_ctx * pipe_ctx)37464b1d0e8SNicholas Kazlauskas void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
37564b1d0e8SNicholas Kazlauskas {
37664b1d0e8SNicholas Kazlauskas bool is_hdmi_tmds;
37764b1d0e8SNicholas Kazlauskas bool is_dp;
37864b1d0e8SNicholas Kazlauskas
37964b1d0e8SNicholas Kazlauskas ASSERT(pipe_ctx->stream);
38064b1d0e8SNicholas Kazlauskas
38164b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL)
38264b1d0e8SNicholas Kazlauskas return; /* this is not root pipe */
38364b1d0e8SNicholas Kazlauskas
38464b1d0e8SNicholas Kazlauskas is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
38564b1d0e8SNicholas Kazlauskas is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
38664b1d0e8SNicholas Kazlauskas
387e9cfe00bSNicholas Kazlauskas if (!is_hdmi_tmds && !is_dp)
38864b1d0e8SNicholas Kazlauskas return;
38964b1d0e8SNicholas Kazlauskas
39064b1d0e8SNicholas Kazlauskas if (is_hdmi_tmds)
39164b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
39264b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc,
39364b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame);
39498ce7d32SWenjing Liu else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
395d5a43956SWenjing Liu pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(
396d5a43956SWenjing Liu pipe_ctx->stream_res.hpo_dp_stream_enc,
397d5a43956SWenjing Liu &pipe_ctx->stream_res.encoder_info_frame);
398d5a43956SWenjing Liu return;
399d5a43956SWenjing Liu } else {
400e95afc1cSSung Joon Kim if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
401e95afc1cSSung Joon Kim pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
402e95afc1cSSung Joon Kim pipe_ctx->stream_res.stream_enc,
403e95afc1cSSung Joon Kim &pipe_ctx->stream_res.encoder_info_frame);
404e95afc1cSSung Joon Kim
40564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
40664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc,
40764b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame);
40864b1d0e8SNicholas Kazlauskas }
40964b1d0e8SNicholas Kazlauskas }
dcn31_z10_save_init(struct dc * dc)410f586fea8SJake Wang void dcn31_z10_save_init(struct dc *dc)
411f586fea8SJake Wang {
412f586fea8SJake Wang union dmub_rb_cmd cmd;
413f586fea8SJake Wang
414f586fea8SJake Wang memset(&cmd, 0, sizeof(cmd));
415f586fea8SJake Wang cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
416f586fea8SJake Wang cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;
417f586fea8SJake Wang
418e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
419f586fea8SJake Wang }
42064b1d0e8SNicholas Kazlauskas
dcn31_z10_restore(const struct dc * dc)421ac02dc34SEric Yang void dcn31_z10_restore(const struct dc *dc)
42264b1d0e8SNicholas Kazlauskas {
42364b1d0e8SNicholas Kazlauskas union dmub_rb_cmd cmd;
42464b1d0e8SNicholas Kazlauskas
42564b1d0e8SNicholas Kazlauskas /*
42664b1d0e8SNicholas Kazlauskas * DMUB notifies whether restore is required.
42764b1d0e8SNicholas Kazlauskas * Optimization to avoid sending commands when not required.
42864b1d0e8SNicholas Kazlauskas */
42964b1d0e8SNicholas Kazlauskas if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
43064b1d0e8SNicholas Kazlauskas return;
43164b1d0e8SNicholas Kazlauskas
43264b1d0e8SNicholas Kazlauskas memset(&cmd, 0, sizeof(cmd));
43364b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
43464b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
43564b1d0e8SNicholas Kazlauskas
436e97cc04fSJosip Pavic dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
43764b1d0e8SNicholas Kazlauskas }
43864b1d0e8SNicholas Kazlauskas
dcn31_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)43964b1d0e8SNicholas Kazlauskas void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
44064b1d0e8SNicholas Kazlauskas {
44164b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1;
44264b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2;
4438639bd70SCharlene Liu uint32_t org_ip_request_cntl;
44464b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_hubp_power_gate)
44564b1d0e8SNicholas Kazlauskas return;
44664b1d0e8SNicholas Kazlauskas
44764b1d0e8SNicholas Kazlauskas if (REG(DOMAIN0_PG_CONFIG) == 0)
44864b1d0e8SNicholas Kazlauskas return;
4498639bd70SCharlene Liu REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
4508639bd70SCharlene Liu if (org_ip_request_cntl == 0)
4518639bd70SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
45264b1d0e8SNicholas Kazlauskas
45364b1d0e8SNicholas Kazlauskas switch (hubp_inst) {
45464b1d0e8SNicholas Kazlauskas case 0:
45564b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
45664b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
45764b1d0e8SNicholas Kazlauskas break;
45864b1d0e8SNicholas Kazlauskas case 1:
45964b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
46064b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
46164b1d0e8SNicholas Kazlauskas break;
46264b1d0e8SNicholas Kazlauskas case 2:
46364b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
46464b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
46564b1d0e8SNicholas Kazlauskas break;
46664b1d0e8SNicholas Kazlauskas case 3:
46764b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
46864b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
46964b1d0e8SNicholas Kazlauskas break;
47064b1d0e8SNicholas Kazlauskas default:
47164b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER();
47264b1d0e8SNicholas Kazlauskas break;
47364b1d0e8SNicholas Kazlauskas }
4748639bd70SCharlene Liu if (org_ip_request_cntl == 0)
4758639bd70SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
47664b1d0e8SNicholas Kazlauskas }
47764b1d0e8SNicholas Kazlauskas
dcn31_init_sys_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_phy_addr_space_config * pa_config)47864b1d0e8SNicholas Kazlauskas int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
47964b1d0e8SNicholas Kazlauskas {
48064b1d0e8SNicholas Kazlauskas struct dcn_hubbub_phys_addr_config config;
48164b1d0e8SNicholas Kazlauskas
48264b1d0e8SNicholas Kazlauskas config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
48364b1d0e8SNicholas Kazlauskas config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
48464b1d0e8SNicholas Kazlauskas config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
48564b1d0e8SNicholas Kazlauskas config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
48664b1d0e8SNicholas Kazlauskas config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
48764b1d0e8SNicholas Kazlauskas config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
48864b1d0e8SNicholas Kazlauskas config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
48964b1d0e8SNicholas Kazlauskas config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
49064b1d0e8SNicholas Kazlauskas
49164b1d0e8SNicholas Kazlauskas if (pa_config->gart_config.base_addr_is_mc_addr) {
49264b1d0e8SNicholas Kazlauskas /* Convert from MC address to offset into FB */
49364b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
49464b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_base +
49564b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_offset;
49664b1d0e8SNicholas Kazlauskas } else
49764b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
49864b1d0e8SNicholas Kazlauskas
49964b1d0e8SNicholas Kazlauskas return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
50064b1d0e8SNicholas Kazlauskas }
50164b1d0e8SNicholas Kazlauskas
dcn31_reset_back_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)50264b1d0e8SNicholas Kazlauskas static void dcn31_reset_back_end_for_pipe(
50364b1d0e8SNicholas Kazlauskas struct dc *dc,
50464b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx,
50564b1d0e8SNicholas Kazlauskas struct dc_state *context)
50664b1d0e8SNicholas Kazlauskas {
50764b1d0e8SNicholas Kazlauskas struct dc_link *link;
50864b1d0e8SNicholas Kazlauskas
50964b1d0e8SNicholas Kazlauskas DC_LOGGER_INIT(dc->ctx->logger);
51064b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL) {
51164b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL;
51264b1d0e8SNicholas Kazlauskas return;
51364b1d0e8SNicholas Kazlauskas }
51464b1d0e8SNicholas Kazlauskas ASSERT(!pipe_ctx->top_pipe);
51564b1d0e8SNicholas Kazlauskas
51664b1d0e8SNicholas Kazlauskas dc->hwss.set_abm_immediate_disable(pipe_ctx);
51764b1d0e8SNicholas Kazlauskas
51864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_dsc_config(
51964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg,
52064b1d0e8SNicholas Kazlauskas OPTC_DSC_DISABLED, 0, 0);
52164b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
52264b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
52364b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
52464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
52564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
526*49b4cab7SAlvin Lee if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
5279c75891fSWenjing Liu pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
52864b1d0e8SNicholas Kazlauskas
52964b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_drr)
53064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_drr(
53164b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, NULL);
53264b1d0e8SNicholas Kazlauskas
53364b1d0e8SNicholas Kazlauskas link = pipe_ctx->stream->link;
53464b1d0e8SNicholas Kazlauskas /* DPMS may already disable or */
53564b1d0e8SNicholas Kazlauskas /* dpms_off status is incorrect due to fastboot
53664b1d0e8SNicholas Kazlauskas * feature. When system resume from S4 with second
53764b1d0e8SNicholas Kazlauskas * screen only, the dpms_off would be true but
53864b1d0e8SNicholas Kazlauskas * VBIOS lit up eDP, so check link status too.
53964b1d0e8SNicholas Kazlauskas */
5409c75891fSWenjing Liu if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
54198ce7d32SWenjing Liu dc->link_srv->set_dpms_off(pipe_ctx);
5429c75891fSWenjing Liu else if (pipe_ctx->stream_res.audio)
54364b1d0e8SNicholas Kazlauskas dc->hwss.disable_audio_stream(pipe_ctx);
54464b1d0e8SNicholas Kazlauskas
54564b1d0e8SNicholas Kazlauskas /* free acquired resources */
54664b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.audio) {
54764b1d0e8SNicholas Kazlauskas /*disable az_endpoint*/
54864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
54964b1d0e8SNicholas Kazlauskas
55064b1d0e8SNicholas Kazlauskas /*free audio*/
55164b1d0e8SNicholas Kazlauskas if (dc->caps.dynamic_audio == true) {
55264b1d0e8SNicholas Kazlauskas /*we have to dynamic arbitrate the audio endpoints*/
55364b1d0e8SNicholas Kazlauskas /*we free the resource, need reset is_audio_acquired*/
55464b1d0e8SNicholas Kazlauskas update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
55564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, false);
55664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio = NULL;
55764b1d0e8SNicholas Kazlauskas }
55864b1d0e8SNicholas Kazlauskas }
55964b1d0e8SNicholas Kazlauskas
56064b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL;
56164b1d0e8SNicholas Kazlauskas DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
56264b1d0e8SNicholas Kazlauskas pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
56364b1d0e8SNicholas Kazlauskas }
56464b1d0e8SNicholas Kazlauskas
dcn31_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)56564b1d0e8SNicholas Kazlauskas void dcn31_reset_hw_ctx_wrap(
56664b1d0e8SNicholas Kazlauskas struct dc *dc,
56764b1d0e8SNicholas Kazlauskas struct dc_state *context)
56864b1d0e8SNicholas Kazlauskas {
56964b1d0e8SNicholas Kazlauskas int i;
57064b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq;
57164b1d0e8SNicholas Kazlauskas
57264b1d0e8SNicholas Kazlauskas /* Reset Back End*/
57364b1d0e8SNicholas Kazlauskas for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
57464b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx_old =
57564b1d0e8SNicholas Kazlauskas &dc->current_state->res_ctx.pipe_ctx[i];
57664b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
57764b1d0e8SNicholas Kazlauskas
57864b1d0e8SNicholas Kazlauskas if (!pipe_ctx_old->stream)
57964b1d0e8SNicholas Kazlauskas continue;
58064b1d0e8SNicholas Kazlauskas
58164b1d0e8SNicholas Kazlauskas if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
58264b1d0e8SNicholas Kazlauskas continue;
58364b1d0e8SNicholas Kazlauskas
58464b1d0e8SNicholas Kazlauskas if (!pipe_ctx->stream ||
58564b1d0e8SNicholas Kazlauskas pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
58664b1d0e8SNicholas Kazlauskas struct clock_source *old_clk = pipe_ctx_old->clock_source;
58764b1d0e8SNicholas Kazlauskas
58864b1d0e8SNicholas Kazlauskas dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
58964b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_stream_gating)
590ae6c9601SYi-Ling Chen hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
59164b1d0e8SNicholas Kazlauskas if (old_clk)
59264b1d0e8SNicholas Kazlauskas old_clk->funcs->cs_power_down(old_clk);
59364b1d0e8SNicholas Kazlauskas }
59464b1d0e8SNicholas Kazlauskas }
5950d4b4253SJimmy Kizito
5960d4b4253SJimmy Kizito /* New dc_state in the process of being applied to hardware. */
5976b6d12b6SJimmy Kizito link_enc_cfg_set_transient_mode(dc, dc->current_state, context);
59864b1d0e8SNicholas Kazlauskas }
5990a068b68SJake Wang
dcn31_setup_hpo_hw_control(const struct dce_hwseq * hws,bool enable)6000a068b68SJake Wang void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
6010a068b68SJake Wang {
6020a068b68SJake Wang if (hws->ctx->dc->debug.hpo_optimization)
6030a068b68SJake Wang REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
6040a068b68SJake Wang }
605