Searched refs:REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (Results 1 – 2 of 2) sorted by relevance
1158 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c macro
481 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0, in hdmi_8996_pll_set_clk_rate()