Searched refs:REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 (Results 1 – 2 of 2) sorted by relevance
1030 #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038 macro
445 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E); in hdmi_8996_pll_set_clk_rate()