Searched refs:REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL (Results 1 – 2 of 2) sorted by relevance
942 #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050 macro
422 hdmi_phy_write(phy, REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL, 0x0F); in hdmi_8996_pll_set_clk_rate()