Searched refs:REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL (Results 1 – 2 of 2) sorted by relevance
940 #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c macro
421 hdmi_phy_write(phy, REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL, 0x0F); in hdmi_8996_pll_set_clk_rate()