Searched refs:REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK (Results 1 – 2 of 2) sorted by relevance
595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
8073 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 macro