Searched refs:REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP (Results 1 – 2 of 2) sorted by relevance
299 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 macro
223 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); in a6xx_gmu_start()