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Searched refs:REGV_WR32 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_37xx.c290 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in ivpu_boot_host_ss_rst_clr_assert()
307 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); in ivpu_boot_host_ss_rst_drive()
324 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); in ivpu_boot_host_ss_clk_drive()
412 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); in ivpu_boot_host_ss_axi_drive()
445 REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
520 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); in ivpu_boot_dpu_active_drive()
580 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
794 REGV_WR32(MTL_VPU_CPU_SS_TIM_WDOG_EN, 0); in ivpu_hw_37xx_wdt_disable()
799 REGV_WR32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, val); in ivpu_hw_37xx_wdt_disable()
887 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); in ivpu_hw_37xx_irq_disable()
[all …]
H A Divpu_hw_40xx.c282 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); in ivpu_boot_host_ss_rst_drive()
299 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); in ivpu_boot_host_ss_clk_drive()
374 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in ivpu_boot_idle_gen_drive()
410 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); in ivpu_boot_host_ss_axi_drive()
450 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
518 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); in ivpu_boot_pwr_island_isolation_drive()
543 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
608 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val); in ivpu_boot_soc_cpu_drive()
921 REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0); in ivpu_hw_40xx_wdt_disable()
925 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val); in ivpu_hw_40xx_wdt_disable()
[all …]
H A Divpu_mmu.c385 REGV_WR32(reg, val); in ivpu_mmu_reg_write()
450 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_PROD, q->prod); in ivpu_mmu_cmdq_sync()
507 REGV_WR32(VPU_37XX_HOST_MMU_CR1, val); in ivpu_mmu_reset()
510 REGV_WR32(VPU_37XX_HOST_MMU_STRTAB_BASE_CFG, mmu->strtab.base_cfg); in ivpu_mmu_reset()
513 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_PROD, 0); in ivpu_mmu_reset()
514 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_CONS, 0); in ivpu_mmu_reset()
534 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_PROD_SEC, 0); in ivpu_mmu_reset()
535 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_CONS_SEC, 0); in ivpu_mmu_reset()
808 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_CONS_SEC, evtq->cons); in ivpu_mmu_get_event()
869 REGV_WR32(VPU_37XX_HOST_MMU_GERRORN, gerror_val); in ivpu_mmu_irq_gerr_handler()
H A Divpu_hw_reg_io.h27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) macro