290 	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);  in ivpu_boot_host_ss_rst_clr_assert()
307 	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);  in ivpu_boot_host_ss_rst_drive()
324 	REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);  in ivpu_boot_host_ss_clk_drive()
399 	REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0);  in ivpu_boot_vpu_idle_gen_disable()
412 	REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);  in ivpu_boot_host_ss_axi_drive()
445 	REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val);  in ivpu_boot_host_ss_top_noc_drive()
474 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);  in ivpu_boot_pwr_island_trickle_drive()
486 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);  in ivpu_boot_pwr_island_drive()
508 	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);  in ivpu_boot_pwr_island_isolation_drive()
520 	REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);  in ivpu_boot_dpu_active_drive()
568 	REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);  in ivpu_boot_no_snoop_enable()
580 	REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);  in ivpu_boot_tbu_mmu_enable()
591 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);  in ivpu_boot_soc_cpu_boot()
594 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);  in ivpu_boot_soc_cpu_boot()
597 	REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);  in ivpu_boot_soc_cpu_boot()
600 	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);  in ivpu_boot_soc_cpu_boot()
603 	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);  in ivpu_boot_soc_cpu_boot()
789 	REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);  in ivpu_hw_37xx_wdt_disable()
790 	REGV_WR32(MTL_VPU_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);  in ivpu_hw_37xx_wdt_disable()
793 	REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);  in ivpu_hw_37xx_wdt_disable()
794 	REGV_WR32(MTL_VPU_CPU_SS_TIM_WDOG_EN, 0);  in ivpu_hw_37xx_wdt_disable()
799 	REGV_WR32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, val);  in ivpu_hw_37xx_wdt_disable()
866 	REGV_WR32(MTL_VPU_CPU_SS_TIM_IPC_FIFO, vpu_addr);  in ivpu_hw_37xx_reg_ipc_tx_set()
876 	REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);  in ivpu_hw_37xx_irq_enable()
887 	REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);  in ivpu_hw_37xx_irq_disable()
917 	REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);  in ivpu_hw_37xx_irqv_handler()