282 	REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);  in ivpu_boot_host_ss_rst_drive()
299 	REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);  in ivpu_boot_host_ss_clk_drive()
374 	REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);  in ivpu_boot_idle_gen_drive()
410 	REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);  in ivpu_boot_host_ss_axi_drive()
450 	REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);  in ivpu_boot_host_ss_top_noc_drive()
479 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);  in ivpu_boot_pwr_island_trickle_drive()
494 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);  in ivpu_boot_pwr_island_drive()
518 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);  in ivpu_boot_pwr_island_isolation_drive()
529 	REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);  in ivpu_boot_no_snoop_enable()
543 	REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);  in ivpu_boot_tbu_mmu_enable()
608 	REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);  in ivpu_boot_soc_cpu_drive()
646 	REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);  in ivpu_boot_soc_cpu_boot()
917 	REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);  in ivpu_hw_40xx_wdt_disable()
918 	REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);  in ivpu_hw_40xx_wdt_disable()
920 	REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);  in ivpu_hw_40xx_wdt_disable()
921 	REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);  in ivpu_hw_40xx_wdt_disable()
925 	REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);  in ivpu_hw_40xx_wdt_disable()
976 	REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);  in ivpu_hw_40xx_reg_ipc_tx_set()
986 	REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);  in ivpu_hw_40xx_irq_enable()
997 	REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);  in ivpu_hw_40xx_irq_disable()
1026 	REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);  in ivpu_hw_40xx_irqv_handler()