Home
last modified time | relevance | path

Searched refs:R4 (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/tests/tcg/multiarch/
H A Dsha1.c67 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
112 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
113 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
114 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
115 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
116 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/
H A Dtune-cortexr4.inc2 # Tune Settings for Cortex-R4
6 TUNEVALID[cortexr4] = "Enable Cortex-R4 specific processor optimizations"
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr208 | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
/openbmc/libcper/include/libcper/
H A DCper.h1534 UINT32 R4; member
/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc896 .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/python3-requests-toolbelt/
H A D090856f4159c40a2927fb88546419f2e1697ad5f.patch977 …fDUB4x1Mtcnwi9mzFpQj+UuDHGv7kbh88OI2iqdyAl0+mCITTspdnDjiUwyTohsT1020OoLoy+7R4+V4ThXU2sxGjFoP7DwHAM…
1105 …fDUB4x1Mtcnwi9mzFpQj+UuDHGv7kbh88OI2iqdyAl0+mCITTspdnDjiUwyTohsT1020OoLoy+7R4+V4ThXU2sxGjFoP7DwHAM…
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex956 r4 & uint64 & Register R4. \texttt{UINT32} value null extended to \texttt{UINT64}.\\
/openbmc/u-boot/
H A DREADME4654 R3-R4: parameter passing and return values