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Searched refs:PTU (Results 1 – 25 of 35) sorted by relevance

12

/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero_mux_data.h19 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
20 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
21 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
22 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
23 {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
66 {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */
67 {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */
68 {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */
76 {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */
79 {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */
[all …]
/openbmc/u-boot/board/compulab/cm_t54/
H A Dmux.c18 {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
19 {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
30 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
31 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
32 {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
33 {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
34 {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
42 {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */
46 {HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */
63 {I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */
[all …]
/openbmc/u-boot/board/ti/omap5_uevm/
H A Dmux_data.h15 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
16 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
17 {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
18 {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
19 {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
20 {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
21 {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
22 {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
23 {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
24 {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
[all …]
/openbmc/u-boot/board/ti/panda/
H A Dpanda_mux_data.h37 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
38 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
39 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
40 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
41 {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
42 {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
43 {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
44 {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
65 {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
73 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
[all …]
/openbmc/u-boot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
26 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
36 {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
55 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
[all …]
/openbmc/u-boot/board/overo/
H A Dovero.h40 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
41 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
42 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
44 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
46 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
48 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
95 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
118 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
119 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
131 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
[all …]
H A Dcommon.c81 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
82 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
83 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
84 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
85 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
86 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
87 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
88 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
89 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
121 MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
[all …]
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h21 { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
22 { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
23 { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
39 { I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */
40 { I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */
42 { I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */
43 { I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */
45 { I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */
46 { I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */
48 { I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */
[all …]
/openbmc/u-boot/board/technexion/tao3530/
H A Dtao3530.h69 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
70 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
71 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
72 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
73 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
74 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
75 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
76 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
79 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
65 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
67 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/technexion/twister/
H A Dtwister.h91 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
97 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
98 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
99 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
101 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/htkw/mcx/
H A Dmcx.h77 MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
78 MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
79 MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
80 MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
81 MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
82 MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
83 MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
84 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
85 MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
86 MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
[all …]
/openbmc/u-boot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h87 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
97 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.h107 MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
108 MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
109 MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
110 MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
114 MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
115 MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
116 MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
117 MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
118 MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
119 MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/logicpd/omap3som/
H A Domap3logic.h88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in set_muxconf_regs()
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in set_muxconf_regs()
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in set_muxconf_regs()
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in set_muxconf_regs()
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in set_muxconf_regs()
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in set_muxconf_regs()
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in set_muxconf_regs()
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in set_muxconf_regs()
96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in set_muxconf_regs()
98 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/8dtech/eco5pk/
H A Deco5pk.h79 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
80 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
81 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
82 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h104 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
105 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
153 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
154 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
156 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
183 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
184 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
194 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
195 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
254 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
[all …]
/openbmc/u-boot/board/logicpd/am3517evm/
H A Dam3517evm.h82 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
[all …]
/openbmc/u-boot/board/ti/evm/
H A Devm.h88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
98 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
[all …]
/openbmc/u-boot/board/compulab/cm_t35/
H A Dcm_t35.c169 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in cm_t3x_set_common_muxconf()
170 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in cm_t3x_set_common_muxconf()
171 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in cm_t3x_set_common_muxconf()
172 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in cm_t3x_set_common_muxconf()
173 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in cm_t3x_set_common_muxconf()
174 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in cm_t3x_set_common_muxconf()
175 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in cm_t3x_set_common_muxconf()
176 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in cm_t3x_set_common_muxconf()
177 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in cm_t3x_set_common_muxconf()
179 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ in cm_t3x_set_common_muxconf()
[all …]
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.h100 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
101 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
102 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
149 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
150 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
152 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
179 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
180 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
190 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
191 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
[all …]
/openbmc/u-boot/board/ti/am3517crane/
H A Dam3517crane.h83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
89 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
92 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
101 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
222 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
241 MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
[all …]
/openbmc/u-boot/board/corscience/tricorder/
H A Dtricorder.h77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
96 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
144 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
145 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
147 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
174 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
175 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
185 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
186 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
[all …]
/openbmc/u-boot/board/timll/devkit8000/
H A Ddevkit8000.h99 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
100 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
101 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
102 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
147 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
148 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
150 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
177 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
178 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
188 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
[all …]
/openbmc/u-boot/board/isee/igep00x0/
H A Digep00x0.h83 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
84 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
99 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
100 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
109 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
110 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
111 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
112 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
121 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
123 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
[all …]

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