53 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
57 	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
58 	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
59 	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
60 	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
61 	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
62 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
63 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
64 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
65 	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
66 	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
67 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
68 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
69 	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
70 	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
71 	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
72 	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
73 	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
74 	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
75 	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
76 	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
77 	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
78 	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
79 	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
80 	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
81 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
82 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
83 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
86 	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
88 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | DIS  | M4));/*GPIO_54*/  in set_muxconf_regs()
90 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | DIS  | M4));/*GPIO_58*/  in set_muxconf_regs()
93 	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTU | EN  | M4)); /*GPIO_59*/  in set_muxconf_regs()
97 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
99 	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTU | EN  | M4)); /*GPIO_61*/  in set_muxconf_regs()
101 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
103 	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)); /*GPIO_65*/  in set_muxconf_regs()
109 	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | EN  | M4)); /*GPIO_163*/  in set_muxconf_regs()
111 	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)); /*GPIO_164*/  in set_muxconf_regs()
114 	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M4)); /*GPIO_144*/  in set_muxconf_regs()
123 	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
124 	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
125 	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
126 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
127 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
128 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
161 	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
162 	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
163 	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
164 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
167 	MUX_VAL(CP(CCDC_WEN),		(IDIS | PTU | EN  | M4)); /*GPIO_98*/  in set_muxconf_regs()
172 	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  | PTU | EN  | M0));  in set_muxconf_regs()
181 	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTU | DIS | M0));  in set_muxconf_regs()
184 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/  in set_muxconf_regs()
190 	MUX_VAL(CP(MCBSP1_FSX),		(IEN | PTU | EN  | M1)); /*MCSPI4_CS0*/  in set_muxconf_regs()
192 	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/  in set_muxconf_regs()
197 	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTU | DIS | M4)); /*GPIO_162*/  in set_muxconf_regs()
213 	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/  in set_muxconf_regs()
226 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/  in set_muxconf_regs()
229 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTU | DIS | M4)); /*GPIO_2*/  in set_muxconf_regs()
230 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTU | DIS | M4)); /*GPIO_3*/  in set_muxconf_regs()
231 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTU | DIS | M4)); /*GPIO_4*/  in set_muxconf_regs()
232 	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTU | DIS | M4)); /*GPIO_5*/  in set_muxconf_regs()
233 	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTU | DIS | M4)); /*GPIO_6*/  in set_muxconf_regs()
234 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTU | DIS | M4)); /*GPIO_7*/  in set_muxconf_regs()