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/openbmc/linux/Documentation/powerpc/
H A Ddawr-power9.rst2 DAWR issues on POWER9
5 On older POWER9 processors, the Data Address Watchpoint Register (DAWR) can
17 cpu : POWER9, altivec supported
33 For ptrace, we now advertise zero breakpoints on POWER9 via the
38 guest on a POWER9 host. Current Linux guests ignore this error, so
42 actually set it on POWER9 hardware. This is done so we don't break
43 migration from POWER8 to POWER9, at the cost of silently losing the
51 For GDB watchpoints (ie 'watch' command) on POWER9 bare metal , GDB
56 The same will also be true for any guests started on a POWER9
63 guest is migrated to a POWER9 host, the watchpoint will be lost on the
[all …]
H A Dcpu_families.rst13 - Radix MMU (POWER9 and later)
109 | POWER9 |
H A Dtransactional_memory.rst205 POWER9 chapter
208 TM on POWER9 has issues with storing the complete register state. This
214 KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
216 To account for this different POWER9 chips have TM enabled in
245 Guest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and
246 POWER9C DD1.2. Since earlier POWER9 processors don't support TM
247 emulation, migration from POWER8 to POWER9 is not supported there.
/openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/
H A D0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch21 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
25 -{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
34 +{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|POWER9|POWER10, 0, {WC}},
/openbmc/linux/Documentation/devicetree/bindings/powerpc/opal/
H A Dpower-mgt.txt57 0x00100000 /* This is a fast stop state (POWER9) */
58 0x00200000 /* This is a deep-stop state (POWER9) */
71 respectively by the kernel. On POWER9 this property is required.
76 This property is required on POWER9 and absent on POWER8.
82 required on POWER9 and absent on POWER8.
112 POWER9.
118 property on POWER8 and is absent on POWER9.
/openbmc/linux/Documentation/hwmon/
H A Dibmpowernv.rst44 sub-group. In POWER9, this attribute corresponds to
57 sub-group. In POWER9, this attribute corresponds to
68 sub-group. In POWER9, this attribute corresponds to
79 sub-group. In POWER9, this attribute corresponds to
/openbmc/linux/arch/powerpc/platforms/book3s/
H A DKconfig9 VAS devices are found in POWER9-based and later systems, they
12 and user-mode APIs for the NX-GZIP accelerator on POWER9 PowerNV
/openbmc/openbmc/meta-openpower/recipes-phosphor/host/
H A Dp9-host-start.bb1 SUMMARY = "POWER9 start host"
2 DESCRIPTION = "Service to start POWER9 IPL through SBE"
H A Dp9-cfam-override.bb1 SUMMARY = "POWER9 CFAM override"
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-firmware-opal-sensor-groups4 Description: Sensor groups directory for POWER9 powernv servers
20 In POWER9, the min-max of a sensor is the historical minimum
H A Dsysfs-bus-event_source-devices-caps18 /sys/bus/event_source/devices/cpu/caps/pmu_name:POWER9
H A Dsysfs-bus-platform-devices-occ-hwmon11 POWER9 and up processors over the Self-Boot Engine (SBE) FIFO.
/openbmc/linux/drivers/hwmon/occ/
H A DKconfig21 tristate "POWER9 OCC through SBE"
26 On-Chip Controller (OCC) on a POWER9 processor. However, this driver
/openbmc/openpower-occ-control/
H A DREADME.md43 IBM EnergyScale for POWER9 Processor-Based Systems:
46 OCC Firmware Interface Spec for POWER9:
/openbmc/linux/tools/testing/selftests/powerpc/pmu/sampling_tests/
H A Dmisc.c78 case POWER9: in init_ev_encodes()
132 if ((pvr != POWER10) && (pvr != POWER9)) in platform_check_for_tests()
499 base_pvr = POWER9; in auxv_generic_compat_pmu()
/openbmc/openpower-proc-control/service_files/
H A Dpcie-poweroff@.service.in2 Description=POWER9 PCIe Power-off Workaround
/openbmc/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A Dreserved_bits_mmcra_sample_elig_mode_test.c65 } else if (PVR_VER(mfspr(SPRN_PVR)) == POWER9) { in reserved_bits_mmcra_sample_elig_mode()
H A Dblacklisted_events_test.c84 SKIP_IF(PVR_VER(pvr) != POWER9); in check_for_power9_version()
H A Devent_alternatives_tests_p9.c38 SKIP_IF(PVR_VER(mfspr(SPRN_PVR)) != POWER9); in event_alternatives_tests_p9()
/openbmc/linux/Documentation/virt/kvm/devices/
H A Dxive.rst4 POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)
8 - KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1
12 POWER9 XIVE interrupt controller.
15 requires a POWER9 host and the guest OS should have support for the
/openbmc/linux/Documentation/devicetree/bindings/fsi/
H A Dibm,p9-occ.txt1 Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC)
/openbmc/qemu/docs/system/ppc/
H A Dpowernv.rst18 * Multi processor support for POWER8, POWER8NVL and POWER9.
22 * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
23 * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
96 Six PHBs are defined per chip (POWER9) but no default PCI layout is
H A Dpseries.rst20 - POWER9
27 - POWER9
196 In order to run KVM-PR guests with POWER9 processors, someone will need to start
257 .. [1] On POWER9 DD2.1 processors, the page table format on the host and guest
271 is a feature found on IBM POWER9 and POWER10 processors.
/openbmc/openbmc/poky/meta/conf/machine/include/powerpc/
H A Darch-powerpc64.inc24 QEMU_EXTRAOPTIONS:tune-powerpc64le = " -cpu POWER9"
/openbmc/linux/Documentation/translations/zh_CN/userspace-api/accelerators/
H A Docxl.rst158 注意这只在POWER9上可用。

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