| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rk3128-cru.h | 10 #define PLL_APLL 1 macro
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| H A D | rk3036-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3228-cru.h | 10 #define PLL_APLL 1 macro
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| H A D | rk3188-cru-common.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3288-cru.h | 8 #define PLL_APLL 1 macro
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| H A D | rv1108-cru.h | 11 #define PLL_APLL 0 macro
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| H A D | rk3328-cru.h | 10 #define PLL_APLL 1 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3188-cru-common.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3128-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3228-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rv1108-cru.h | 11 #define PLL_APLL 0 macro
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| H A D | px30-cru.h | 7 #define PLL_APLL 1 macro
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| H A D | rk3308-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3328-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3288-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rockchip,rv1126-cru.h | 65 #define PLL_APLL 1 macro
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| H A D | rk3568-cru.h | 70 #define PLL_APLL 1 macro
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | rk3288-board.c | 120 clk.id = PLL_APLL; in veyron_init()
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| H A D | clk-rk3036.c | 137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| H A D | clk-rk3128.c | 159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| H A D | clk-rk3228.c | 169 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3188.c | 502 case PLL_APLL: in rk3188_clk_set_rate()
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| H A D | clk_rk3288.c | 793 case PLL_APLL: in rk3288_clk_set_rate()
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