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Searched refs:PLLE_BASE (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c657 #define PLLE_BASE 0x0e8 macro
712 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
715 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
734 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
748 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
761 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
763 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c628 #define PLLE_BASE 0x0e8 macro
683 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
686 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
715 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
717 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c942 #define PLLE_BASE 0x0e8 macro
966 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
968 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
993 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1000 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1004 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1006 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1128 #define PLLE_BASE 0x0e8 macro
1182 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1189 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1198 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1200 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20.c60 #define PLLE_BASE 0xe8 macro
407 .base_reg = PLLE_BASE,
H A Dclk-tegra114.c69 #define PLLE_BASE 0xe8 macro
561 .base_reg = PLLE_BASE,
H A Dclk-tegra30.c69 #define PLLE_BASE 0xe8 macro
515 .base_reg = PLLE_BASE,
H A Dclk-tegra124.c58 #define PLLE_BASE 0xe8 macro
477 .base_reg = PLLE_BASE,
H A Dclk-tegra210.c85 #define PLLE_BASE 0xe8 macro
1971 .base_reg = PLLE_BASE,